From f834a4ecc5566a0c90d682222407e03ddfa397c5 Mon Sep 17 00:00:00 2001
From: Martin Preuss <martin@aquamaniac.de>
Date: Sat, 17 May 2025 10:44:37 +0200
Subject: [PATCH 01/13] fixed apidoc.

---
 avr/apps/door/main.asm | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/avr/apps/door/main.asm b/avr/apps/door/main.asm
index ef0bb46..da436e9 100644
--- a/avr/apps/door/main.asm
+++ b/avr/apps/door/main.asm
@@ -49,7 +49,7 @@ AppDoor_Init:
   ldi yl, LOW(appDoorValSchedData)
   ldi yh, HIGH(appDoorValSchedData)
   rcall ValueScheduler_Init
-  ldi r16, (1<<VALSCHED_FLAGS_REPEAT1_BIT)  ; only repeat report interval for active motion
+  ldi r16, (1<<VALSCHED_FLAGS_REPEAT1_BIT)  ; only repeat report interval for open door
   std Y+VALSCHED_OFFS_FLAGS, r16
   
   ret

From d97d2ac08fe41213b9cb1f5b22ffc4aafe793324 Mon Sep 17 00:00:00 2001
From: Martin Preuss <martin@aquamaniac.de>
Date: Sat, 17 May 2025 10:44:48 +0200
Subject: [PATCH 02/13] fixed a bug.

---
 avr/apps/reportsensors/main.asm | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/avr/apps/reportsensors/main.asm b/avr/apps/reportsensors/main.asm
index 94a7dd8..6f4751e 100644
--- a/avr/apps/reportsensors/main.asm
+++ b/avr/apps/reportsensors/main.asm
@@ -53,11 +53,12 @@ AppReportSensors_Fini:
 ;
 
 AppReportSensors_OnEverySecond:
-  in r15, SREG
   push r15
+    in r15, SREG
     cli
     rcall AppReportSensors_OnEverySecond_noIrqs
-  out SREG, r15
+    out SREG, r15
+  pop r15
   ret
 AppReportSensors_OnEverySecond_noIrqs:
   lds r16, reportSensorTimer

From f5606554c9e2e3dc947f91f09602e7fb0d608cf3 Mon Sep 17 00:00:00 2001
From: Martin Preuss <martin@aquamaniac.de>
Date: Sat, 17 May 2025 10:45:37 +0200
Subject: [PATCH 03/13] added tool flashnode.sh

---
 flashnode.sh | 64 ++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 64 insertions(+)
 create mode 100755 flashnode.sh

diff --git a/flashnode.sh b/flashnode.sh
new file mode 100755
index 0000000..bc3358b
--- /dev/null
+++ b/flashnode.sh
@@ -0,0 +1,64 @@
+#!/bin/bash
+
+NODE="$1"
+
+if test -z "$NODE"; then
+  echo "Missing node"
+  exit 1
+fi
+
+
+
+case $NODE in
+  c01)
+       DEVICE_ARG="-p m8515"
+       HFUSE_ARG="-U hfuse:w:0xD1:m"
+       LFUSE_ARG="-U lfuse:w:0xE4:m"
+       FILE_ARG="-U flash:w:./0-build/avr/devices/c01/boot/c01_boot.hex"
+       ;;
+  n21)
+       DEVICE_ARG="-p t84"
+       HFUSE_ARG="-U hfuse:w:0xD7:m"
+       LFUSE_ARG=""
+       EFUSE_ARG="-U efuse:w:0xFE:m"
+       FILE="-U flash:w:./0-build/avr/devices/n21/boot/n21_boot.hex"
+       ;;
+  n22)
+       DEVICE_ARG="-p t85"
+       HFUSE_ARG="-U hfuse:w:0xD7:m"
+       LFUSE_ARG=""
+       EFUSE_ARG="-U efuse:w:0xFE:m"
+       FILE_ARG="-U flash:w:./0-build/avr/devices/n22/boot/n22_boot.hex"
+       ;;
+  n23)
+       DEVICE_ARG="-p t84"
+       HFUSE_ARG="-U hfuse:w:0xD7:m"
+       LFUSE_ARG=""
+       EFUSE_ARG="-U efuse:w:0xFE:m"
+       FILE_ARG="-U flash:w:./0-build/avr/devices/n21/boot/n21_boot.hex"
+       ;;
+  n24)
+       DEVICE_ARG="-p t84"
+       HFUSE_ARG="-U hfuse:w:0xD7:m"
+       LFUSE_ARG=""
+       EFUSE_ARG="-U efuse:w:0xFE:m"
+       FILE_ARG="-U flash:w:./0-build/avr/devices/n23/boot/n23_boot.hex"
+       ;;
+  t03)
+       DEVICE_ARG="-p t841"
+       HFUSE_ARG="-U hfuse:w:0xD7:m"
+       LFUSE_ARG=""
+       EFUSE_ARG="-U efuse:w:0xFE:m"
+       FILE_ARG="-U flash:w:./0-build/avr/devices/t03/boot/t03_boot.hex"
+       ;;
+  *)
+       echo "Unknown node $NODE".
+       exit 1
+       ;;
+esac
+
+
+echo "avrdude -c stk500 -P /dev/ttyACM0 -B16 $DEVICE_ARG $HFUSE_ARG $LFUSE_ARG $EFUSE_ARG $FILE_ARG"
+avrdude -c stk500 -P /dev/ttyACM0 -B16 $DEVICE_ARG $HFUSE_ARG $LFUSE_ARG $EFUSE_ARG $FILE_ARG
+
+

From bb4e16cae7d0e66d12a902574b63a6958c7bf970 Mon Sep 17 00:00:00 2001
From: Martin Preuss <martin@aquamaniac.de>
Date: Sat, 17 May 2025 10:46:03 +0200
Subject: [PATCH 04/13] add line with ATTN.

---
 aqhome-nodes.sh | 1 +
 1 file changed, 1 insertion(+)

diff --git a/aqhome-nodes.sh b/aqhome-nodes.sh
index 7152686..78b9ca0 100755
--- a/aqhome-nodes.sh
+++ b/aqhome-nodes.sh
@@ -11,3 +11,4 @@ export LD_LIBRARY_PATH="0-build/aqhome/:$LD_LIBRARY_PATH"
 
 # 0-build/apps/aqhomed/aqhomed -l aqhome.log -db aqhome.db -p aqhomed.pid -W /tmp/aqhome/aqhomed -ma 192.168.117.192 -mp 1883 -t 127.0.0.1 --mqttclientid=AQHOMEMQTTLOGTEST1
 0-build/apps/aqhome-nodes/aqhome-nodes -N -l aqhome-nodes.log -db aqhome-nodes.db -p aqhome-nodes.pid -t 127.0.0.1 -ba 127.0.0.1 "$@"
+#0-build/apps/aqhome-nodes/aqhome-nodes -l aqhome-nodes.log -db aqhome-nodes.db -p aqhome-nodes.pid -t 127.0.0.1 -ba 127.0.0.1 "$@"

From 930229b96994a539b35838cf05188a20a587bfd3 Mon Sep 17 00:00:00 2001
From: Martin Preuss <martin@aquamaniac.de>
Date: Sat, 17 May 2025 10:46:46 +0200
Subject: [PATCH 05/13] add macros for reading/writing IO regs regardless of
 their position (i.e. < or >=0x40).

---
 avr/common/0BUILD       |  1 +
 avr/common/utils_io.asm | 29 +++++++++++++++++++++++++++++
 2 files changed, 30 insertions(+)
 create mode 100644 avr/common/utils_io.asm

diff --git a/avr/common/0BUILD b/avr/common/0BUILD
index 4d18df1..26bb9eb 100644
--- a/avr/common/0BUILD
+++ b/avr/common/0BUILD
@@ -17,6 +17,7 @@
     utils_copy_from_flash.asm
     utils_copy_sdram.asm
     utils_initial_wait.asm
+    utils_io.asm
     utils_wait.asm
     utils_wait_fixed.asm
     utils_wait_pin.asm
diff --git a/avr/common/utils_io.asm b/avr/common/utils_io.asm
new file mode 100644
index 0000000..8309a1e
--- /dev/null
+++ b/avr/common/utils_io.asm
@@ -0,0 +1,29 @@
+; ***************************************************************************
+; copyright   : (C) 2023 by Martin Preuss
+; email       : martin@libchipcard.de
+;
+; ***************************************************************************
+; * This file is part of the project "AqHome".                              *
+; * Please see toplevel file COPYING of that project for license details.   *
+; ***************************************************************************
+
+
+; M_IO_READ DEST, SRC
+.macro M_IO_READ
+.if @1 < 64
+  in @0, @1
+.else
+  lds @0, @1
+.endif
+.endmacro
+
+
+
+; M_IO_WRITE DEST, SRC
+.macro M_IO_WRITE
+.if @0 < 64
+  out @0, @1
+.else
+  sts @0, @1
+.endif
+.endmacro

From 732dcd74f70890a87a865492b6de63594a91b79a Mon Sep 17 00:00:00 2001
From: Martin Preuss <martin@aquamaniac.de>
Date: Sat, 17 May 2025 10:47:29 +0200
Subject: [PATCH 06/13] only include "sendvalue.asm" if networking code
 enabled.

---
 avr/devices/all/includes.asm | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/avr/devices/all/includes.asm b/avr/devices/all/includes.asm
index a526ebc..55160d6 100644
--- a/avr/devices/all/includes.asm
+++ b/avr/devices/all/includes.asm
@@ -11,7 +11,9 @@
 .include "devices/all/main.asm"
 .include "devices/all/apps.asm"
 .include "devices/all/modules.asm"
-.include "devices/all/sendvalue.asm"
+#ifdef MODULES_NETWORK
+ .include "devices/all/sendvalue.asm"
+#endif
 .include "devices/all/data.asm"
 
 .include "common/utils.asm"

From dba503df5bcd7583379772ee3436a697ff097301 Mon Sep 17 00:00:00 2001
From: Martin Preuss <martin@aquamaniac.de>
Date: Sat, 17 May 2025 10:47:44 +0200
Subject: [PATCH 07/13] only call LedSimple_OnPacketReceived is networking code
 enabled.

---
 avr/devices/all/modules.asm | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/avr/devices/all/modules.asm b/avr/devices/all/modules.asm
index 04592d4..90a41f6 100644
--- a/avr/devices/all/modules.asm
+++ b/avr/devices/all/modules.asm
@@ -203,7 +203,9 @@ mainModulesOnPacketReceived:
 #endif
 
 #ifdef MODULES_LED_SIMPLE
+  #ifdef MODULES_NETWORK
     rcall LedSimple_OnPacketReceived
+  #endif  
 #endif
 
 

From d51ca9b1d1cba054374bd2241ef31f493123e225 Mon Sep 17 00:00:00 2001
From: Martin Preuss <martin@aquamaniac.de>
Date: Sat, 17 May 2025 10:47:59 +0200
Subject: [PATCH 08/13] n21: added VALUE_ID_LEDSIMPLE_TIMING

---
 avr/devices/n21/main/main.asm | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/avr/devices/n21/main/main.asm b/avr/devices/n21/main/main.asm
index c9c0c62..a2e0325 100644
--- a/avr/devices/n21/main/main.asm
+++ b/avr/devices/n21/main/main.asm
@@ -97,6 +97,8 @@
 
 ;.equ VALUE_ID_REED_CONF    = 0x81
 
+.equ VALUE_ID_LEDSIMPLE_TIMING = 0x88
+
 
 
 ; ***************************************************************************

From e545251b27003176f5f8560542fb0dcdb8074405 Mon Sep 17 00:00:00 2001
From: Martin Preuss <martin@aquamaniac.de>
Date: Sat, 17 May 2025 10:48:39 +0200
Subject: [PATCH 09/13] moved timer setup code into hardware include file.

---
 avr/devices/all/hw_tn84.asm    | 58 ++++++++++++++++++++++++++++++++++
 avr/devices/all/hw_tn841.asm   | 58 ++++++++++++++++++++++++++++++++++
 avr/devices/all/hw_tn85.asm    | 58 ++++++++++++++++++++++++++++++++++
 avr/modules/basetimer/main.asm | 50 +----------------------------
 4 files changed, 175 insertions(+), 49 deletions(-)

diff --git a/avr/devices/all/hw_tn84.asm b/avr/devices/all/hw_tn84.asm
index 3218867..b093245 100644
--- a/avr/devices/all/hw_tn84.asm
+++ b/avr/devices/all/hw_tn84.asm
@@ -85,3 +85,61 @@ systemSleep:
 
 
 
+; ---------------------------------------------------------------------------
+; @routine systemSetupTimer0
+;
+
+systemSetupTimer0:            ; setup timer for IRQ every 100ms
+  ldi r16, (1<<CS02) | (0<<CS01) | (1<<CS00)  ; Prescaler 1024
+  out TCCR0B, r16
+  
+  ldi r16, (1<<WGM01) | (0<<WGM00)             ; CTC mode
+  out TCCR0A, r16
+
+; Settings for clock 1Mhz (default)
+; use timer0 with OCR0A=98-1 (irq every 97.65625 millisecs), baseTimerModuleReloadValue 1
+;
+.if clock == 1000000
+  ; CMP-A interrupt about every 100ms
+  ldi r16, 98-1      ; (1,000,000/1024)/10 = 97.65625
+  out OCR0A, r16
+
+  ldi r16, 1
+  sts baseTimerModuleReloadValue, r16
+  sts baseTimerModuleTickCounter, r16
+.endif
+
+;
+; Settings for clock 8Mhz
+; use timer0 with OCR0A=78 (irq every 9.984 millisecs), baseTimerModuleReloadValue 10
+;
+.if clock == 8000000
+  ; CMP-A interrupt about every 10ms
+  ldi r16, 78-1
+  out OCR0A, r16
+
+  ldi r16, 10
+  sts baseTimerModuleReloadValue, r16
+  sts baseTimerModuleTickCounter, r16
+.endif
+
+
+  ldi r16, (1<<OCF0A)             ; clear pending interrupts
+.ifdef TIFR0
+  out TIFR0, r16
+.else
+  out TIFR, r16
+.endif
+  
+  ldi r16, (1<<OCIE0A)            ; Timer/Counter0 Output Compare Match A Interrupt Enable
+.ifdef TIMSK0
+  out TIMSK0, r16
+.else
+  out TIMSK, r16
+.endif
+  sec
+  ret
+; @end
+
+
+
diff --git a/avr/devices/all/hw_tn841.asm b/avr/devices/all/hw_tn841.asm
index 1a4d300..1804319 100644
--- a/avr/devices/all/hw_tn841.asm
+++ b/avr/devices/all/hw_tn841.asm
@@ -77,3 +77,61 @@ systemSleep:
 
 
 
+; ---------------------------------------------------------------------------
+; @routine systemSetupTimer0
+;
+
+systemSetupTimer0:                            ; setup timer for IRQ every 100ms
+  ldi r16, (1<<CS02) | (0<<CS01) | (1<<CS00)  ; Prescaler 1024
+  out TCCR0B, r16
+  
+  ldi r16, (1<<WGM01) | (0<<WGM00)             ; CTC mode
+  out TCCR0A, r16
+
+; Settings for clock 1Mhz (default)
+; use timer0 with OCR0A=98-1 (irq every 97.65625 millisecs), baseTimerModuleReloadValue 1
+;
+.if clock == 1000000
+  ; CMP-A interrupt about every 100ms
+  ldi r16, 98-1      ; (1,000,000/1024)/10 = 97.65625
+  out OCR0A, r16
+
+  ldi r16, 1
+  sts baseTimerModuleReloadValue, r16
+  sts baseTimerModuleTickCounter, r16
+.endif
+
+;
+; Settings for clock 8Mhz
+; use timer0 with OCR0A=78 (irq every 9.984 millisecs), baseTimerModuleReloadValue 10
+;
+.if clock == 8000000
+  ; CMP-A interrupt about every 10ms
+  ldi r16, 78-1
+  out OCR0A, r16
+
+  ldi r16, 10
+  sts baseTimerModuleReloadValue, r16
+  sts baseTimerModuleTickCounter, r16
+.endif
+
+
+  ldi r16, (1<<OCF0A)             ; clear pending interrupts
+.ifdef TIFR0
+  out TIFR0, r16
+.else
+  out TIFR, r16
+.endif
+  
+  ldi r16, (1<<OCIE0A)            ; Timer/Counter0 Output Compare Match A Interrupt Enable
+.ifdef TIMSK0
+  out TIMSK0, r16
+.else
+  out TIMSK, r16
+.endif
+  sec
+  ret
+; @end
+
+
+
diff --git a/avr/devices/all/hw_tn85.asm b/avr/devices/all/hw_tn85.asm
index 420f6b7..acaa936 100644
--- a/avr/devices/all/hw_tn85.asm
+++ b/avr/devices/all/hw_tn85.asm
@@ -84,4 +84,62 @@ systemSleep:
 
 
 
+; ---------------------------------------------------------------------------
+; @routine systemSetupTimer0
+;
+
+systemSetupTimer0:            ; setup timer for IRQ every 100ms
+  ldi r16, (1<<CS02) | (0<<CS01) | (1<<CS00)  ; Prescaler 1024
+  out TCCR0B, r16
+  
+  ldi r16, (1<<WGM01) | (0<<WGM00)             ; CTC mode
+  out TCCR0A, r16
+
+; Settings for clock 1Mhz (default)
+; use timer0 with OCR0A=98-1 (irq every 97.65625 millisecs), baseTimerModuleReloadValue 1
+;
+.if clock == 1000000
+  ; CMP-A interrupt about every 100ms
+  ldi r16, 98-1      ; (1,000,000/1024)/10 = 97.65625
+  out OCR0A, r16
+
+  ldi r16, 1
+  sts baseTimerModuleReloadValue, r16
+  sts baseTimerModuleTickCounter, r16
+.endif
+
+;
+; Settings for clock 8Mhz
+; use timer0 with OCR0A=78 (irq every 9.984 millisecs), baseTimerModuleReloadValue 10
+;
+.if clock == 8000000
+  ; CMP-A interrupt about every 10ms
+  ldi r16, 78-1
+  out OCR0A, r16
+
+  ldi r16, 10
+  sts baseTimerModuleReloadValue, r16
+  sts baseTimerModuleTickCounter, r16
+.endif
+
+
+  ldi r16, (1<<OCF0A)             ; clear pending interrupts
+.ifdef TIFR0
+  out TIFR0, r16
+.else
+  out TIFR, r16
+.endif
+  
+  ldi r16, (1<<OCIE0A)            ; Timer/Counter0 Output Compare Match A Interrupt Enable
+.ifdef TIMSK0
+  out TIMSK0, r16
+.else
+  out TIMSK, r16
+.endif
+  sec
+  ret
+; @end
+
+
+
 
diff --git a/avr/modules/basetimer/main.asm b/avr/modules/basetimer/main.asm
index 7b83e17..077defc 100644
--- a/avr/modules/basetimer/main.asm
+++ b/avr/modules/basetimer/main.asm
@@ -51,55 +51,7 @@ BaseTimer_Init:            ; setup timer for IRQ every 100ms
   ldi r17, (baseTimerModuleData_end-baseTimerModuleData)
   rcall Utils_FillSram
 
-  ldi r16, (1<<CS02) | (0<<CS01) | (1<<CS00)  ; Prescaler 1024
-  out TCCR0B, r16
-  
-  ldi r16, (1<<WGM01) | (0<<WGM00)             ; CTC mode
-  out TCCR0A, r16
-
-
-;
-; Settings for clock 1Mhz (default)
-; use timer0 with OCR0A=98-1 (irq every 97.65625 millisecs), baseTimerModuleReloadValue 1
-;
-.if clock == 1000000
-  ; CMP-A interrupt about every 100ms
-  ldi r16, 98-1      ; (1,000,000/1024)/10 = 97.65625
-  out OCR0A, r16
-
-  ldi r16, 1
-  sts baseTimerModuleReloadValue, r16
-  sts baseTimerModuleTickCounter, r16
-.endif
-
-;
-; Settings for clock 8Mhz
-; use timer0 with OCR0A=78 (irq every 9.984 millisecs), baseTimerModuleReloadValue 10
-;
-.if clock == 8000000
-  ; CMP-A interrupt about every 10ms
-  ldi r16, 78-1
-  out OCR0A, r16
-
-  ldi r16, 10
-  sts baseTimerModuleReloadValue, r16
-  sts baseTimerModuleTickCounter, r16
-.endif
-
-
-  ldi r16, (1<<OCF0A)             ; clear pending interrupts
-.ifdef TIFR0
-  out TIFR0, r16
-.else
-  out TIFR, r16
-.endif
-  
-  ldi r16, (1<<OCIE0A)            ; Timer/Counter0 Output Compare Match A Interrupt Enable
-.ifdef TIMSK0
-  out TIMSK0, r16
-.else
-  out TIMSK, r16
-.endif
+  rcall systemSetupTimer0
   sec
   ret
 ; @end

From 5a46db37c14b686e6658d0ca2b8191f6d5f20079 Mon Sep 17 00:00:00 2001
From: Martin Preuss <martin@aquamaniac.de>
Date: Sat, 17 May 2025 10:49:03 +0200
Subject: [PATCH 10/13] bootloader: decreased waiting time.

---
 avr/modules/bootloader/main.asm | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/avr/modules/bootloader/main.asm b/avr/modules/bootloader/main.asm
index e295abf..6f8dfb0 100644
--- a/avr/modules/bootloader/main.asm
+++ b/avr/modules/bootloader/main.asm
@@ -66,13 +66,13 @@ bootLoader:
   brcc bootLoader_waitAndRestartBootLoader
   ; try to start firmware
 bootLoader_startFirmware:
-  ldi r19, 20 ; loop count
+  ldi r19, 10 ; loop count
   ldi r20, 4  ; on time
   ldi r21, 1  ; off time
   rcall bootLoaderBlinkLed
   rjmp firmwareStart
 bootLoader_waitAndRestartBootLoader:
-  ldi r19, 15 ; loop count
+  ldi r19, 5 ; loop count
   ldi r20, 1  ; on time
   ldi r21, 8  ; off time
   rcall bootLoaderBlinkLed

From 21c2c60f4fb86f1efb01989ea605b038753698a1 Mon Sep 17 00:00:00 2001
From: Martin Preuss <martin@aquamaniac.de>
Date: Sat, 17 May 2025 10:50:09 +0200
Subject: [PATCH 11/13] started working on AtMega8515 module C1.

---
 avr/common/utils.asm                    |  18 +
 avr/devices/0BUILD                      |   1 +
 avr/devices/all/0BUILD                  |   1 +
 avr/devices/all/defs.asm                |   3 +-
 avr/devices/all/hw_m8515.asm            | 151 ++++++++
 avr/devices/c01/.gitignore              |   2 +
 avr/devices/c01/0BUILD                  |  22 ++
 avr/devices/c01/README                  |  10 +
 avr/devices/c01/aqua_c01.xml            |  11 +
 avr/devices/c01/boot/0BUILD             |  32 ++
 avr/devices/c01/boot/boot.asm           | 163 ++++++++
 avr/devices/c01/defs.asm                | 108 ++++++
 avr/devices/c01/main/0BUILD             |  34 ++
 avr/devices/c01/main/data.asm           |  14 +
 avr/devices/c01/main/main.asm           | 231 +++++++++++
 avr/modules/flash/0BUILD                |   2 +
 avr/modules/flash/eeprom.asm            |   4 +
 avr/modules/flash/flash1p.asm           |  11 +
 avr/modules/flash/flash1pmega.asm       |  81 ++++
 avr/modules/flash/flashprocess.asm      |   1 +
 avr/modules/flash/flashxp.asm           |   8 +
 avr/modules/flash/io_attn.asm           |  41 ++
 avr/modules/flash/io_bitbang.asm        |  43 +-
 avr/modules/flash/io_uart.asm           |  32 ++
 avr/modules/flash/io_uart1.asm          | 386 +-----------------
 avr/modules/flash/io_uart_all.asm       | 387 ++++++++++++++++++
 avr/modules/flash/io_uart_all_attn.asm  | 495 ++++++++++++++++++++++++
 avr/modules/uart_hw/comonuart0.asm      |  15 +-
 avr/modules/uart_hw/m_lowlevel_uart.asm |   8 +-
 29 files changed, 1893 insertions(+), 422 deletions(-)
 create mode 100644 avr/devices/all/hw_m8515.asm
 create mode 100644 avr/devices/c01/.gitignore
 create mode 100644 avr/devices/c01/0BUILD
 create mode 100644 avr/devices/c01/README
 create mode 100644 avr/devices/c01/aqua_c01.xml
 create mode 100644 avr/devices/c01/boot/0BUILD
 create mode 100644 avr/devices/c01/boot/boot.asm
 create mode 100644 avr/devices/c01/defs.asm
 create mode 100644 avr/devices/c01/main/0BUILD
 create mode 100644 avr/devices/c01/main/data.asm
 create mode 100644 avr/devices/c01/main/main.asm
 create mode 100644 avr/modules/flash/flash1pmega.asm
 create mode 100644 avr/modules/flash/io_uart.asm
 create mode 100644 avr/modules/flash/io_uart_all.asm
 create mode 100644 avr/modules/flash/io_uart_all_attn.asm

diff --git a/avr/common/utils.asm b/avr/common/utils.asm
index e297b9b..d8db6a8 100644
--- a/avr/common/utils.asm
+++ b/avr/common/utils.asm
@@ -269,7 +269,11 @@ Utils_IncrementCounter16:
 ; MODIFIED REGISTERS: R16
 
 Utils_ReadEepromIncr:
+.ifdef EEPE
   sbic EECR, EEPE          ; wait for previous write to complete (if any)
+.else
+  sbic EECR, EEWE          ; wait for previous write to complete (if any)
+.endif
     rjmp Utils_ReadEepromIncr
   out EEARH, xh            ; set EEPROM address
   out EEARL, xl
@@ -293,15 +297,29 @@ Utils_ReadEepromIncr:
 ; MODIFIED REGISTERS: R17
 
 Utils_WriteEepromIncr:
+.ifdef EEPE
   sbic EECR, EEPE          ; wait for previous write to complete (if any)
+.else
+  sbic EECR, EEWE          ; wait for previous write to complete (if any)
+.endif
     rjmp Utils_WriteEepromIncr
+.ifdef EEPM1
   ldi r17, (0<<EEPM1) | (0<<EEPM0) ; set programming mode
+.endif
   out EECR, r17
   out EEARH, xh                    ; set EEPROM address
   out EEARL, xl
   out EEDR,  r16                   ; write data to data register
+.ifdef EEMPE
   sbi EECR, EEMPE                  ; write logical one to EEMPE
+.else
+  sbi EECR, EEMWE                  ; write logical one to EEMWE
+.endif
+.ifdef EEPE
   sbi EECR, EEPE                   ; start EEPROM write by setting EEPE
+.else
+  sbi EECR, EEWE                   ; start EEPROM write by setting EEWE
+.endif
   adiw xh:xl, 1
   ret
 
diff --git a/avr/devices/0BUILD b/avr/devices/0BUILD
index 85b3625..8dad59d 100644
--- a/avr/devices/0BUILD
+++ b/avr/devices/0BUILD
@@ -24,6 +24,7 @@
 
   <subdirs>
     all
+    c01
     n16
     n21
     n22
diff --git a/avr/devices/all/0BUILD b/avr/devices/all/0BUILD
index b63c66d..72eda57 100644
--- a/avr/devices/all/0BUILD
+++ b/avr/devices/all/0BUILD
@@ -9,6 +9,7 @@
     hw_tn84.asm
     hw_tn85.asm
     hw_tn841.asm
+    hw_m8515.asm
     includes.asm
     main.asm
     modules.asm
diff --git a/avr/devices/all/defs.asm b/avr/devices/all/defs.asm
index ae0861a..c3b0a1d 100644
--- a/avr/devices/all/defs.asm
+++ b/avr/devices/all/defs.asm
@@ -40,7 +40,8 @@
 
 .equ EEPROM_OFFS_SEED                  = 10   ; 2 bytes
 
-.equ EEPROM_OFFS_REED_CONF             = 12   ; 1 byte (plus one byte reserved)
+.equ EEPROM_OFFS_OSCCAL_SLOW           = 12   ; 1 byte
+.equ EEPROM_OFFS_OSCCAL_FAST           = 13   ; 1 byte
 
 .equ EEPROM_OFFS_MAL_CONF_ONTIME       = 14 ; 2 bytes
 .equ EEPROM_OFFS_MAL_CONF_SRC1_ADDR    = 16 ; 1 byte
diff --git a/avr/devices/all/hw_m8515.asm b/avr/devices/all/hw_m8515.asm
new file mode 100644
index 0000000..8df7e0e
--- /dev/null
+++ b/avr/devices/all/hw_m8515.asm
@@ -0,0 +1,151 @@
+; ***************************************************************************
+; copyright   : (C) 2025 by Martin Preuss
+; email       : martin@libchipcard.de
+;
+; ***************************************************************************
+; * This file is part of the project "AqHome".                              *
+; * Please see toplevel file COPYING of that project for license details.   *
+; ***************************************************************************
+
+; Hardware routine  for AtTiny 84 devices
+
+
+.cseg
+
+
+; ---------------------------------------------------------------------------
+; @routine systemInitHardware
+;
+
+systemInitHardware:
+  ; set all ports as inputs and enable internal pull-up resistors
+  ldi r16, 0xff
+  clr r17
+.ifdef PORTA
+  out DDRA, r17  ; all input
+  out PORTA, r16 ; enable pull-up on all
+.endif
+
+.ifdef PORTB
+  out DDRB, r17  ; all input
+  out PORTB, r16 ; enable pull-up on all
+.endif
+
+.ifdef PORTC
+  out DDRC, r17  ; all input
+  out PORTC, r16 ; enable pull-up on all
+.endif
+
+.ifdef PORTD
+  out DDRD, r17  ; all input
+  out PORTD, r16 ; enable pull-up on all
+.endif
+
+.ifdef PORTE
+  out DDRE, r17  ; all input
+  out PORTE, r16 ; enable pull-up on all
+.endif
+
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine systemSetSpeed
+;
+
+systemSetSpeed:
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine systemSleep
+;
+
+systemSleep:
+  ; only modify SE, SM2, SM1 and SM0
+  cli
+  M_IO_READ r16, MCUCR
+  cbr r16, (1<<SE) | (1<<SM2) | (1<<SM1)
+  M_IO_WRITE MCUCR, r16
+  M_IO_READ r16, EMCUCR
+  cbr r16, (1<<SM0)
+  M_IO_WRITE EMCUCR, r16
+  sei                        ; make sure interrupts really are enabled
+  M_IO_READ r16, MCUCR       ; enable sleep mode
+  sbr r16, (1<<SE)
+  M_IO_WRITE MCUCR, r16
+  sleep                      ; sleep, wait for interrupt
+  M_IO_READ r16, MCUCR       ; disable sleep mode
+  cbr r16, (1<<SE)
+  M_IO_WRITE MCUCR, r16
+  ret
+; @end
+
+
+
+
+
+; ---------------------------------------------------------------------------
+; @routine systemSetupTimer0
+;
+
+systemSetupTimer0:            ; setup timer for IRQ every 100ms
+  ldi r16, (1<<CS02) | (0<<CS01) | (1<<CS00) | (1<<WGM01) | (0<<WGM00)  ; Prescaler 1024, CTC mode
+  out TCCR0, r16
+
+;
+; Settings for clock 1Mhz (default)
+; use timer0 with OCR0A=98-1 (irq every 97.65625 millisecs), baseTimerModuleReloadValue 1
+;
+.if clock == 1000000
+  ; CMP-A interrupt about every 100ms
+  ldi r16, 98-1      ; (1,000,000/1024)/10 = 97.65625
+  out OCR0, r16
+
+  ldi r16, 1
+  sts baseTimerModuleReloadValue, r16
+  sts baseTimerModuleTickCounter, r16
+.endif
+
+;
+; Settings for clock 8Mhz
+; use timer0 with OCR0=78 (irq every 9.984 millisecs), baseTimerModuleReloadValue 10
+;
+.if clock == 8000000
+  ; CMP interrupt about every 10ms
+  ldi r16, 78-1
+  out OCR0, r16
+
+  ldi r16, 10
+  sts baseTimerModuleReloadValue, r16
+  sts baseTimerModuleTickCounter, r16
+.endif
+
+  ldi r16, (1<<OCF0)              ; clear pending interrupts
+.ifdef TIFR0
+  out TIFR0, r16
+.else
+  out TIFR, r16
+.endif
+  
+.ifdef TIMSK0
+  M_IO_READ r16, TIMSK0
+  sbr r16, (1<<OCIE0)        ; Timer/Counter0 Output Compare Match A Interrupt Enable
+  M_IO_WRITE TIMSK0, r16
+.else
+  M_IO_READ r16, TIMSK
+  sbr r16, (1<<OCIE0)        ; Timer/Counter0 Output Compare Match A Interrupt Enable
+  M_IO_WRITE TIMSK, r16
+.endif
+
+  sec
+  ret
+; @end
+
+
+
+
diff --git a/avr/devices/c01/.gitignore b/avr/devices/c01/.gitignore
new file mode 100644
index 0000000..8e0618c
--- /dev/null
+++ b/avr/devices/c01/.gitignore
@@ -0,0 +1,2 @@
+*.eep.hex
+*.obj
diff --git a/avr/devices/c01/0BUILD b/avr/devices/c01/0BUILD
new file mode 100644
index 0000000..dc1bfd9
--- /dev/null
+++ b/avr/devices/c01/0BUILD
@@ -0,0 +1,22 @@
+<?xml?>
+
+<gwbuild>
+
+  <subdirs>
+    boot
+    main
+  </subdirs>
+
+  <data dist="true" install="$(datadir)/aqhome/devices/nodes">
+    aqua_c01.xml
+  </data>
+
+  <extradist>
+    defs.asm
+    README
+  </extradist>
+  
+
+</gwbuild>
+
+
diff --git a/avr/devices/c01/README b/avr/devices/c01/README
new file mode 100644
index 0000000..0513f8f
--- /dev/null
+++ b/avr/devices/c01/README
@@ -0,0 +1,10 @@
+
+C01
+===
+
+- Role: Controller with Display
+- MCU: AtMega 8515
+- Connection: RJ45
+- Periphery:
+  - Display with SPI
+
diff --git a/avr/devices/c01/aqua_c01.xml b/avr/devices/c01/aqua_c01.xml
new file mode 100644
index 0000000..4ea15e0
--- /dev/null
+++ b/avr/devices/c01/aqua_c01.xml
@@ -0,0 +1,11 @@
+
+<device name="aqua_c01" driver="nodes">
+  <manufacturer>AQUA</manufacturer>
+  <devicetype>N</devicetype>
+  <deviceversion>1</deviceversion>
+  
+  <values>
+    <value name="LEDTIMING"    id="0x88" type="actor"  dataType="uint16" />
+  </values>
+
+</device>
diff --git a/avr/devices/c01/boot/0BUILD b/avr/devices/c01/boot/0BUILD
new file mode 100644
index 0000000..bfe939f
--- /dev/null
+++ b/avr/devices/c01/boot/0BUILD
@@ -0,0 +1,32 @@
+<?xml?>
+
+<gwbuild>
+
+  <target type="AvrHexFile" name="c01_boot" >
+
+    <includes type="avrasm" >
+      -I $(builddir)
+      -I $(srcdir)
+      -I $(topsrcdir)/avr
+      -I $(topbuilddir)/avr
+    </includes>
+
+
+    <sources type="avrasm" >
+      boot.asm
+    </sources>
+
+
+  </target>
+
+
+  <subdirs>
+  </subdirs>
+
+  <extradist>
+  </extradist>
+  
+
+</gwbuild>
+
+
diff --git a/avr/devices/c01/boot/boot.asm b/avr/devices/c01/boot/boot.asm
new file mode 100644
index 0000000..c681ea6
--- /dev/null
+++ b/avr/devices/c01/boot/boot.asm
@@ -0,0 +1,163 @@
+; ***************************************************************************
+; Source file for base system node on AtMega 8515
+;
+; This is for the maintenance system (i.e. the flash loader).
+;
+; All definitions and changes should go into this file.
+; ***************************************************************************
+
+.equ clock=8000000 ; Define the clock frequency
+
+.nolist
+.include "include/m8515def.inc" ; Define device ATmega8515
+.list
+
+.include "../defs.asm"
+.include "defs_all.asm"
+
+.include "common/utils_wait.asm"
+.include "common/utils_io.asm"
+.include "modules/com2/defs.asm"
+.include "modules/comproto/defs.asm"
+
+
+
+; ***************************************************************************
+; defines
+
+; ---------------------------------------------------------------------------
+; generic
+
+
+.equ NET_BUFFERS_NUM            = 6
+.equ NET_BUFFERS_SIZE           = 32
+
+
+
+; ---------------------------------------------------------------------------
+; firmware settings
+
+.equ FIRMWARE_VERSION_MAJOR       = 0
+.equ FIRMWARE_VERSION_MINOR       = 0
+.equ FIRMWARE_VERSION_PATCHLEVEL  = 1
+
+
+
+; ---------------------------------------------------------------------------
+; LED
+
+.equ LED_DDR             = DDRE
+.equ LED_PORT            = PORTE
+.equ LED_PIN             = PINE
+.equ LED_PINNUM          = PORTE2
+
+
+
+
+
+; ***************************************************************************
+; code segment
+
+.cseg
+.org 0x0000
+
+
+
+; ---------------------------------------------------------------------------
+; Reset and interrupt vectors
+  rjmp main ;  1: Reset vector   RESET
+  reti      ;  2: INT0           External Interrupt Request 0
+  reti      ;  3: INT1           External Interrupt Request 1
+  reti      ;  4: TIMER1_CAPT    Timer/Counter1 Capture Event
+  reti      ;  5: TIMER1_COMPA   Timer/Counter1 Compare Match A
+  reti      ;  6: TIMER1_COMPB   Timer/Counter1 Compare Match B
+  reti      ;  7: TIMER1_OVF     Timer/Counter1 Overflow
+  reti      ;  8: TIMER0_OVF     Timer/Counter0 Overflow
+  reti      ;  9: SPI_STC        Serial Transfer Complete
+  reti      ; 10: USART_RXC      USART Rx Complete
+  reti      ; 11: USART_UDRE     USART Data Register Empty
+  reti      ; 12: USART_TXC      USART Tx Complete
+  reti      ; 13: ANA_COMP       Analog Comparator
+  reti      ; 14: INT2           External Interrupt Request 2
+  reti      ; 15: TIMER0_COMP    Timer/Counter0 Compare Match
+  reti      ; 16: EE_RDY         EEPROM Ready
+  reti      ; 17: SPM_RDY        Store Program Memory Ready
+
+
+
+; ---------------------------------------------------------------------------
+; Device Info Block
+
+devInfoBlock:        ; 12 bytes
+devInfoManufacturer: .db 'A', 'Q', 'U', 'A'
+devInfoId:           .db DEVICEINFO_ID, 0
+devInfoVersion:      .db DEVICEINFO_VERSION, DEVICEINFO_REVISION             ; version, revision
+firmwareVersion:     .db FIRMWARE_VARIANT_BOOT, FIRMWARE_VERSION_MAJOR
+                     .db FIRMWARE_VERSION_MINOR, FIRMWARE_VERSION_PATCHLEVEL
+
+firmwareStart:
+  rjmp main       ; will be overwritten when flashing
+
+
+
+; ***************************************************************************
+; main code
+
+
+.org BOOTLOADER_ADDR
+
+
+main:
+  ldi r16, 0xb0   ; orig: a0
+  out OSCCAL, r16
+  rjmp bootLoader ; this routine is in modules/bootloader/main.asm
+
+
+
+; ***************************************************************************
+; includes
+
+.include "common/utils_wait_fixed.asm"
+.include "common/utils_copy_from_flash.asm"
+.include "common/utils_copy_sdram.asm"
+
+.include "modules/flash/defs.asm"
+.include "modules/flash/eeprom.asm"
+.include "modules/flash/io.asm"
+.include "modules/flash/io_attn.asm"
+.include "modules/flash/io_uart.asm"
+.include "modules/flash/io_uart_all_attn.asm"
+.include "modules/flash/flash1pmega.asm"
+.include "modules/flash/flashxp.asm"
+.include "modules/flash/flashprocess.asm"
+.include "modules/flash/wait.asm"
+.include "modules/bootloader/main.asm"
+.include "modules/network/msg/defs.asm"
+.include "modules/network/msg/crc.asm"
+
+;.include "common/debug.asm"
+
+
+
+systemSetSpeed:
+#if 0  ; disabled (can't really change clock at runtime)
+.if clock == 8000000
+  ldi r16, (1<<CLKPCE)
+  ldi r17, 0
+  out CLKPR, r16
+  out CLKPR, r17
+.endif
+
+.if clock == 1000000
+  ldi r16, (1<<CLKPCE)
+  ldi r17, (1<<CLKPS1) | (1<<CLKPS0)
+  out CLKPR, r16
+  out CLKPR, r17
+.endif
+#endif
+
+  ret
+
+
+
+
diff --git a/avr/devices/c01/defs.asm b/avr/devices/c01/defs.asm
new file mode 100644
index 0000000..6df1f40
--- /dev/null
+++ b/avr/devices/c01/defs.asm
@@ -0,0 +1,108 @@
+; ***************************************************************************
+; copyright   : (C) 2023 by Martin Preuss
+; email       : martin@libchipcard.de
+;
+; ***************************************************************************
+; * This file is part of the project "AqHome".                              *
+; * Please see toplevel file COPYING of that project for license details.   *
+; ***************************************************************************
+
+
+; ***************************************************************************
+;
+;                                 AtMega8515
+;                                 --------
+;         DEV0        (T0)   PB0  1     40 VCC
+;         DEV1        (T1)   PB1  2     39 PA0 (AD0) SRAM
+;         DEV2        (AIN0) PB2  3     38 PA1 (AD1) SRAM
+;         D_RES       (AIN1) PB3  4     37 PA2 (AD2) SRAM
+;         SPI         (SS)   PB4  5     36 PA3 (AD3) SRAM
+;         SPI         (MOSI) PB5  6     35 PA4 (AD4) SRAM
+;         SPI         (MISO) PB6  7     34 PA5 (AD5) SRAM
+;         SPI         (SCK)  PB7  8     33 PA6 (AD6) SRAM
+;                         /RESET  9     32 PA7 (AD7) SRAM
+;         UART        (RXD)  PD0 10     31 PE0 (INT2)
+;         UART        (TXD)  PD1 11     30 PE1 (ALE) SRAM
+;         ATTN        (INT0) PD2 12     29 PE2 (OC1B) LED
+;         T-IRQ       (INT1) PD3 13     28 PC7 (A15) SRAM
+;         D-DC        (XCK)  PD4 14     27 PC6 (A14) SRAM
+;         D_BACKLIGHT (OC1A) PD5 15     26 PC5 (A13) SRAM
+;         SRAM        (/WR)  PD6 16     25 PC4 (A12) SRAM
+;         SRAM        (/RD)  PD7 17     24 PC3 (A11) SRAM
+;                          XTAL2 18     23 PC2 (A10) SRAM
+;                          XTAL1 19     22 PC1 (A9)  SRAM
+;                            GND 20     21 PC0 (A8)  SRAM
+;                                 --------
+;
+; ***************************************************************************
+
+
+
+.equ BOOTLOADER_ADDR = 0xc00
+
+.equ FIRMWARE_VARIANT_BOOT        = 0
+.equ FIRMWARE_VARIANT_TEMP_WINDOW = 1
+
+.equ DEVICEINFO_ID       = 'C'
+.equ DEVICEINFO_VERSION  = 1
+.equ DEVICEINFO_REVISION = 0
+
+
+
+; ---------------------------------------------------------------------------
+; LED module
+
+.equ LED_SIMPLE_ONTIME  = 1     ; shorter
+.equ LED_SIMPLE_OFFTIME = 50    ; longer
+.equ LED_SIMPLE_DDR     = DDRE
+.equ LED_SIMPLE_PORT    = PORTE
+.equ LED_SIMPLE_PORTIN  = PINE
+.equ LED_SIMPLE_PINNUM  = PORTE2
+
+
+
+; ---------------------------------------------------------------------------
+; COM module
+
+.equ COM_BIT_LENGTH      = 52000 ; 104000ns=9600, 52000ns=19200, 26000ns=38400
+.equ COM_HALFBIT_LENGTH  = 26000 ; see https://de.wikipedia.org/wiki/Universal_Asynchronous_Receiver_Transmitter
+
+.equ COM_ATTN_DDR       = DDRD
+.equ COM_ATTN_INPUT     = PIND
+.equ COM_ATTN_OUTPUT    = PORTD
+.equ COM_ATTN_PIN       = PORTD2
+
+.equ COM_IRQ_ADDR_ATTN   = GICR
+.equ COM_IRQ_BIT_ATTN    = INT0
+.equ COM_IRQ_GIFR_ATTN   = INTF0
+;.equ COM_IRQ_GIMSK_ATTN  = PCIE0
+
+
+
+
+
+; ---------------------------------------------------------------------------
+; ComOnUart module
+
+.equ USART0_DATAREG   = UDR
+.equ UCSR0A = UCSRA
+.equ UCSR0B = UCSRB
+.equ UCSR0C = UCSRC
+.equ UBRR0L = UBRRL
+.equ UBRR0H = UBRRH
+
+.equ UCSZ00 = UCSZ0
+.equ UCSZ01 = UCSZ1
+.equ UDRE0  = UDRE
+.equ RXC0   = RXC
+.equ TXC0   = TXC
+.equ FE0    = FE
+.equ DOR0   = DOR
+.equ UPE0   = UPE
+.equ RXEN0  = RXEN
+.equ TXEN0  = TXEN
+.equ USBS0  = USBS
+.equ RXCIE0 = RXCIE
+.equ UDRIE0 = UDRIE
+
+
diff --git a/avr/devices/c01/main/0BUILD b/avr/devices/c01/main/0BUILD
new file mode 100644
index 0000000..51b5e7d
--- /dev/null
+++ b/avr/devices/c01/main/0BUILD
@@ -0,0 +1,34 @@
+<?xml?>
+
+<gwbuild>
+
+  <target type="AvrHexFile" name="c01_firmware" >
+
+    <includes type="avrasm" >
+      -I $(builddir)
+      -I $(srcdir)
+      -I $(topsrcdir)/avr
+      -I $(topbuilddir)/avr
+    </includes>
+
+
+    <sources type="avrasm" >
+      main.asm
+    </sources>
+
+
+  </target>
+
+
+
+  <subdirs>
+  </subdirs>
+
+  <extradist>
+    data.asm
+  </extradist>
+  
+
+</gwbuild>
+
+
diff --git a/avr/devices/c01/main/data.asm b/avr/devices/c01/main/data.asm
new file mode 100644
index 0000000..31ccc2f
--- /dev/null
+++ b/avr/devices/c01/main/data.asm
@@ -0,0 +1,14 @@
+; ***************************************************************************
+; copyright   : (C) 2025 by Martin Preuss
+; email       : martin@libchipcard.de
+;
+; ***************************************************************************
+; * This file is part of the project "AqHome".                              *
+; * Please see toplevel file COPYING of that project for license details.   *
+; ***************************************************************************
+
+
+
+.dseg
+
+
diff --git a/avr/devices/c01/main/main.asm b/avr/devices/c01/main/main.asm
new file mode 100644
index 0000000..15e8748
--- /dev/null
+++ b/avr/devices/c01/main/main.asm
@@ -0,0 +1,231 @@
+; ***************************************************************************
+; copyright   : (C) 2025 by Martin Preuss
+; email       : martin@libchipcard.de
+;
+; ***************************************************************************
+; * This file is part of the project "AqHome".                              *
+; * Please see toplevel file COPYING of that project for license details.   *
+; ***************************************************************************
+
+
+
+
+; ***************************************************************************
+; Source file for temperature sensor node on AtTiny 84
+;
+; This is for the full system (i.e. not the boot loader).
+;
+; All definitions and changes should go into this file.
+;
+;
+; ***************************************************************************
+
+
+;.equ clock=1000000 ; Define the clock frequency
+.equ clock=8000000 ; Define the clock frequency
+
+
+
+.nolist
+.include "include/m8515def.inc" ; Define device ATmega8515
+.list
+
+.include "../defs.asm"
+.include "./data.asm"
+
+.include "devices/all/defs.asm"
+.include "common/utils_wait.asm"
+.include "common/utils_io.asm"
+
+
+
+; ***************************************************************************
+; defines
+
+; ---------------------------------------------------------------------------
+; generic
+
+.equ NET_BUFFERS_NUM            = 6
+.equ NET_BUFFERS_SIZE           = 32
+
+.equ PROGRAM_SENSOR_INTERVAL_SECS = 60
+.equ PROGRAM_STATS_INTERVAL_MINS = 10
+
+
+
+; ---------------------------------------------------------------------------
+; firmware settings including list of modules used
+
+.equ FIRMWARE_VERSION_MAJOR       = 0
+.equ FIRMWARE_VERSION_MINOR       = 0
+.equ FIRMWARE_VERSION_PATCHLEVEL  = 1
+
+
+; #define MODULES_TIMER
+;#define MODULES_CLOCK
+#define MODULES_LED_SIMPLE
+;#define MODULES_NETWORK
+;#define MODULES_COMONUART0
+;#define MODULES_UART_BITBANG
+;#define MODULES_TWI_MASTER
+;#define MODULES_LCD
+;#define LCD_MINIMAL_FONT
+;#define MODULES_SI7021
+;#define MODULES_SGP30
+;#define MODULES_SGP40
+;#define MODULES_STATS
+;#define MODULES_OWI_MASTER
+;#define MODULES_DS18B20
+;#define MODULES_MOTION
+;#define MODULES_CCS811
+
+;#define APPS_NETWORK
+;#define APPS_MOTION
+;#define APPS_REPORTSENSORS
+;#define APPS_STATS
+
+
+
+; ---------------------------------------------------------------------------
+; defines for values
+
+.equ VALUE_ID_SI7021_TEMP      = 0x01
+.equ VALUE_ID_SI7021_HUM       = 0x02
+
+.equ VALUE_ID_ADC              = 0x03
+;.equ VALUE_ID_DS18B20_TEMP     = 0x06
+.equ VALUE_ID_MOTION           = 0x07
+
+.equ VALUE_ID_SGP40_TVOC       = 0x08
+
+.equ VALUE_ID_SGP30_TVOC       = 0x09
+.equ VALUE_ID_SGP30_CO2        = 0x0a
+
+;.equ VALUE_ID_REED_CONF    = 0x81
+
+.equ VALUE_ID_DEBUG            = 0x7f
+
+.equ VALUE_ID_LEDSIMPLE_TIMING = 0x88
+
+
+
+
+
+; ***************************************************************************
+; code segment
+
+.cseg
+.org 000000
+
+
+
+; ---------------------------------------------------------------------------
+; Reset and interrupt vectors
+  rjmp BOOTLOADER_ADDR          ;  1: Reset vector   RESET
+;  rjmp ComOnUart0_AttnChangeIsr ;  2: INT0           External Interrupt Request 0
+  reti
+  reti                          ;  3: INT1           External Interrupt Request 1
+  reti                          ;  4: TIMER1_CAPT    Timer/Counter1 Capture Event
+  reti                          ;  5: TIMER1_COMPA   Timer/Counter1 Compare Match A
+  reti                          ;  6: TIMER1_COMPB   Timer/Counter1 Compare Match B
+  reti                          ;  7: TIMER1_OVF     Timer/Counter1 Overflow
+  reti                          ;  8: TIMER0_OVF     Timer/Counter0 Overflow
+  reti                          ;  9: SPI_STC        Serial Transfer Complete
+;  rjmp ComOnUart0_RxCharIsr     ; 10: USART_RXC      USART Rx Complete
+  reti
+;  rjmp ComOnUart0_TxUdreIsr     ; 11: USART_UDRE     USART Data Register Empty
+  reti
+;  rjmp ComOnUart0_TxCharIsr     ; 12: USART_TXC      USART Tx Complete
+  reti
+  reti                          ; 13: ANA_COMP       Analog Comparator
+  reti                          ; 14: INT2           External Interrupt Request 2
+  rjmp baseTimerIrqOC0A         ; 15: TIMER0_COMP    Timer/Counter0 Compare Match
+  reti                          ; 16: EE_RDY         EEPROM Ready
+  reti                          ; 17: SPM_RDY        Store Program Memory Ready
+
+
+
+devInfoBlock:        ; 12 bytes
+devInfoManufacturer: .db 'A', 'Q', 'U', 'A'
+devInfoId:           .db DEVICEINFO_ID, 0
+devInfoVersion:      .db DEVICEINFO_VERSION, DEVICEINFO_REVISION             ; version, revision
+firmwareVersion:     .db FIRMWARE_VARIANT_TEMP_WINDOW, FIRMWARE_VERSION_MAJOR
+                     .db FIRMWARE_VERSION_MINOR, FIRMWARE_VERSION_PATCHLEVEL
+
+
+
+; ---------------------------------------------------------------------------
+; @routine firmwareStart @global
+
+firmwareStart:
+  rjmp main
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine onSystemStart
+
+onSystemStart:
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine onMessageReceived
+;
+; Called on every message received
+
+onMessageReceived:
+  clc
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine onEvery100ms
+;
+; Called every 100ms. Add your routine calls here. No arguments, no results.
+
+onEvery100ms:
+onEverySecond:
+onEveryMinute:
+onEveryHour:
+onEveryDay:
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine onEveryLoop
+;
+; Called on every loop (i.e. after awakening from sleep).
+;
+onEveryLoop:
+  ret
+; @end
+
+
+
+
+
+; ***************************************************************************
+; includes
+
+.include "devices/all/hw_m8515.asm"
+.include "devices/all/includes.asm"
+
+.include "common/debug.asm"
+
+
+
+; ---------------------------------------------------------------------------
+; defines for network interface
+
+;.equ netInterfaceData = comonuart0_iface
+
+
+
diff --git a/avr/modules/flash/0BUILD b/avr/modules/flash/0BUILD
index 64d9cef..53f3762 100644
--- a/avr/modules/flash/0BUILD
+++ b/avr/modules/flash/0BUILD
@@ -12,7 +12,9 @@
     io.asm
     io_attn.asm
     io_bitbang.asm
+    io_uart.asm
     io_uart1.asm
+    io_uart_all.asm
     wait.asm
   </extradist>
 
diff --git a/avr/modules/flash/eeprom.asm b/avr/modules/flash/eeprom.asm
index 5c6f909..a215953 100644
--- a/avr/modules/flash/eeprom.asm
+++ b/avr/modules/flash/eeprom.asm
@@ -21,7 +21,11 @@
 ; REGS: R16
 
 flashReadEepromIncr:
+.ifdef EEPE
   sbic EECR, EEPE          ; wait for previous write to complete (if any)
+.else
+  sbic EECR, EEWE          ; wait for previous write to complete (if any)
+.endif
     rjmp flashReadEepromIncr
   out EEARH, xh            ; set EEPROM address
   out EEARL, xl
diff --git a/avr/modules/flash/flash1p.asm b/avr/modules/flash/flash1p.asm
index 9e64ffc..ba5c6c0 100644
--- a/avr/modules/flash/flash1p.asm
+++ b/avr/modules/flash/flash1p.asm
@@ -56,6 +56,17 @@ flash1pWritePages_loop:
   ; transfer data from temporary page buffer into FLASH memory
   ldi r20, (1<<PGWRT) + (1<<SPMEN)          ; enable next SPM, write page (R1/R0 ignored)
   rcall flashDoSpm                          ; (R16)
+
+#if 0
+.ifdef RWWSRE
+flash1pWritePages_endLoop:
+    in r20, SPMCR
+    sbrc r20, RWWSB
+  rjmp flash1pWritePages_endLoop
+  ldi r20, (1<<RWWSRE) | (1<<SPMEN)         ; reenable RWW
+  rcall flashDoSpm                          ; (R16)
+.endif
+#endif
   ret
 ; @end
 
diff --git a/avr/modules/flash/flash1pmega.asm b/avr/modules/flash/flash1pmega.asm
new file mode 100644
index 0000000..2066e18
--- /dev/null
+++ b/avr/modules/flash/flash1pmega.asm
@@ -0,0 +1,81 @@
+; ***************************************************************************
+; copyright   : (C) 2025 by Martin Preuss
+; email       : martin@libchipcard.de
+;
+; ***************************************************************************
+; * This file is part of the project "AqHome".                              *
+; * Please see toplevel file COPYING of that project for license details.   *
+; ***************************************************************************
+
+
+.equ FLASH_PAGESIZE = (PAGESIZE*2)
+
+
+; ***************************************************************************
+; data
+
+.dseg
+
+  flashPageStart:   .byte 2
+  flashPageBuffer:  .byte FLASH_PAGESIZE
+
+
+
+; ***************************************************************************
+; code
+
+.cseg
+
+
+
+; ---------------------------------------------------------------------------
+; flash1pMegaWritePage
+;
+; Interrupts must be disabled!
+;
+; @clobbers r0, r1, r20, r24, r25, X, Z
+
+flash1pMegaWritePage:
+  lds zl, flashPageStart
+  lds zh, flashPageStart+1
+  ; copy from SDRAM into MCUs temporary page buffer
+  ldi xl, LOW(flashPageBuffer)
+  ldi xh, HIGH(flashPageBuffer)
+  ldi r24, LOW(PAGESIZE)
+flash1pMegaWritePages_loop:
+    ld r0, X+                               ; read source data from buffer (low)
+    ld r1, X+                               ; read source data from buffer (high)
+    ldi r20, (1<<SPMEN)                     ; enable next SPM, write R1:R0 into temp page buffer
+    rcall flashDoSpm                        ; (R16)
+    adiw zh:zl, 2
+    dec r24
+  brne flash1pMegaWritePages_loop
+
+  subi zl, LOW(PAGESIZE*2)                  ; point back to begin of page
+  sbci zh, HIGH(PAGESIZE*2)
+  ; transfer data from temporary page buffer into FLASH memory
+  ldi r20, (1<<PGWRT) + (1<<SPMEN)          ; enable next SPM, write page (R1/R0 ignored)
+  rcall flashDoSpm                          ; (R16)
+
+  rcall flash1pMegaEnableRWW
+;flash1pMegaWritePages_endLoop:
+;    in r20, SPMCR
+;    sbrc r20, RWWSB
+;  rjmp flash1pMegaWritePages_endLoop
+;  ldi r20, (1<<RWWSRE) | (1<<SPMEN)         ; reenable RWW
+;  rcall flashDoSpm                          ; (R16)
+  ret
+; @end
+
+
+flash1pMegaEnableRWW:
+  ldi r20, (1<<RWWSRE) | (1<<SPMEN)         ; reenable RWW
+  rcall flashDoSpm                          ; (R16)
+  ret
+
+
+
+
+.equ flashWritePage = flash1pMegaWritePage
+
+
diff --git a/avr/modules/flash/flashprocess.asm b/avr/modules/flash/flashprocess.asm
index 182825e..dfc11a5 100644
--- a/avr/modules/flash/flashprocess.asm
+++ b/avr/modules/flash/flashprocess.asm
@@ -117,6 +117,7 @@ flashProcessHandleFlashStart:
   rcall flashWaitFor100ms                    ; TODO: Shorten wait time!!
   clr r16
   rcall flashProcessSendFlashResponse        ; (R15, R16, R17, R18, R19, R20, R21, R22, X)
+
   sec
 flashProcessHandleFlashStart_notMe:
   ret
diff --git a/avr/modules/flash/flashxp.asm b/avr/modules/flash/flashxp.asm
index 0d30037..de805cd 100644
--- a/avr/modules/flash/flashxp.asm
+++ b/avr/modules/flash/flashxp.asm
@@ -292,11 +292,19 @@ flashErasePage:
 
 flashDoSpm:
 flashDoSpm_wait:         ; wait for possibly previous SPM to complete
+.ifdef SPMCSR
     in r16, SPMCSR
+.else
+    in r16, SPMCR
+.endif
     sbrc r16, SPMEN
   rjmp flashDoSpm_wait
   ; SPM timed sequence
+.ifdef SPMCSR
   out SPMCSR, r20
+.else
+  out SPMCR, r20
+.endif
   spm
   ret
 ; @end
diff --git a/avr/modules/flash/io_attn.asm b/avr/modules/flash/io_attn.asm
index 244c5a6..5f745a6 100644
--- a/avr/modules/flash/io_attn.asm
+++ b/avr/modules/flash/io_attn.asm
@@ -94,4 +94,45 @@ ioWaitForAttnState1ms_stateReached:
 
 
 
+; ---------------------------------------------------------------------------
+; @routine ioRawWaitForOneBitLength
+;
+; wait for one bit length (minus cycles for call and ret).
+;
+; @clobbers r22
+
+ioRawWaitForOneBitLength:
+  Utils_WaitNanoSecs COM_BIT_LENGTH, 7, r22       ; wait for one bit duration (minus RCALL/RET)
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine ioRawAcquireBus
+;
+; Reserve bus if free (otherwise return error)
+; Expects interrupts to be disabled.
+;
+; @return CFLAG set if okay (bus acquired), cleared on error
+; @clobbers: none
+
+ioRawAcquireBus:
+  ; check for ATTN line: busy?
+  cbi COM_ATTN_DDR, COM_ATTN_PIN                 ; set ATTN as input
+  cbi COM_ATTN_OUTPUT, COM_ATTN_PIN              ; disable pullup on ATTN
+  nop                                            ; needed to sample current input
+  sbis COM_ATTN_INPUT, COM_ATTN_PIN              ; ATTN low?
+    rjmp ioRawAcquireBus_busy                    ; jump if it is
+  sbi COM_ATTN_DDR, COM_ATTN_PIN                 ; set ATTN as output
+  cbi COM_ATTN_OUTPUT, COM_ATTN_PIN              ; set ATTN low
+  sec
+  ret
+ioRawAcquireBus_busy:
+  clc
+  ret
+; @end
+
+
+
 
diff --git a/avr/modules/flash/io_bitbang.asm b/avr/modules/flash/io_bitbang.asm
index 16999a0..a70d919 100644
--- a/avr/modules/flash/io_bitbang.asm
+++ b/avr/modules/flash/io_bitbang.asm
@@ -281,7 +281,7 @@ ioRawReceiveByte_error:
 ; @clobbers R16, R22 (R17, R21, X)
 
 ioRawSendPacket:
-  rcall ioRawAcquireBus
+  rcall ioRawAcquireBus                   ; (none)
   brcc ioRawSendPacket_lineBusyError
   
   rcall ioRawWaitForOneBitLength          ; wait for one bit duration (R22)
@@ -316,47 +316,6 @@ ioRawSendPacket_lineBusyError:
 
 
 
-; ---------------------------------------------------------------------------
-; @routine ioRawAcquireBus
-;
-; Reserve bus if free (otherwise return error)
-; Expects interrupts to be disabled.
-;
-; @return CFLAG set if okay (bus acquired), cleared on error
-; @clobbers: none
-
-ioRawAcquireBus:
-  ; check for ATTN line: busy?
-  cbi COM_ATTN_DDR, COM_ATTN_PIN                 ; set ATTN as input
-  cbi COM_ATTN_OUTPUT, COM_ATTN_PIN              ; disable pullup on ATTN
-  nop                                            ; needed to sample current input
-  sbis COM_ATTN_INPUT, COM_ATTN_PIN              ; ATTN low?
-    rjmp ioRawAcquireBus_busy                    ; jump if it is
-  sbi COM_ATTN_DDR, COM_ATTN_PIN                 ; set ATTN as output
-  cbi COM_ATTN_OUTPUT, COM_ATTN_PIN              ; set ATTN low
-  sec
-  ret
-ioRawAcquireBus_busy:
-  clc
-  ret
-; @end
-
-
-
-; ---------------------------------------------------------------------------
-; @routine ioRawWaitForOneBitLength
-;
-; wait for one bit length (minus cycles for call and ret).
-;
-; @clobbers r22
-
-ioRawWaitForOneBitLength:
-  Utils_WaitNanoSecs COM_BIT_LENGTH, 7, r22       ; wait for one bit duration (minus RCALL/RET)
-  ret
-; @end
-
-
-
 ; ---------------------------------------------------------------------------
 ; @routine ioRawSendByte
 ;
diff --git a/avr/modules/flash/io_uart.asm b/avr/modules/flash/io_uart.asm
new file mode 100644
index 0000000..40abbac
--- /dev/null
+++ b/avr/modules/flash/io_uart.asm
@@ -0,0 +1,32 @@
+; ***************************************************************************
+; copyright   : (C) 2025 by Martin Preuss
+; email       : martin@libchipcard.de
+;
+; ***************************************************************************
+; * This file is part of the project "AqHome".                              *
+; * Please see toplevel file COPYING of that project for license details.   *
+; ***************************************************************************
+
+
+.equ  UART_REG_UDR   = UDR
+.equ  UART_REG_UCSRA = UCSRA
+.equ  UART_REG_UCSRB = UCSRB
+.equ  UART_REG_UCSRC = UCSRC
+.equ  UART_REG_UBRRL = UBRRL
+.equ  UART_REG_UBRRH = UBRRH
+
+.equ  UART_BIT_UCSZ0 = UCSZ0
+.equ  UART_BIT_UCSZ1 = UCSZ1
+.equ  UART_BIT_UDRE  = UDRE
+.equ  UART_BIT_RXC   = RXC
+.equ  UART_BIT_TXC   = TXC
+.equ  UART_BIT_FE    = FE
+.equ  UART_BIT_DOR   = DOR
+.equ  UART_BIT_UPE   = UPE
+.equ  UART_BIT_RXEN  = RXEN
+.equ  UART_BIT_TXEN  = TXEN
+
+
+
+
+
diff --git a/avr/modules/flash/io_uart1.asm b/avr/modules/flash/io_uart1.asm
index 32cc0d1..0c0538b 100644
--- a/avr/modules/flash/io_uart1.asm
+++ b/avr/modules/flash/io_uart1.asm
@@ -8,377 +8,23 @@
 ; ***************************************************************************
 
 
-; ***************************************************************************
-; code
 
-
-.cseg
-
-
-
-; ---------------------------------------------------------------------------
-; @routine ioRawInit
-; Send a message
-;
-; @clobbers r16, r17
-
-ioRawInit:
-  ; set baudrate
-.if clock == 8000000
-  ldi r16, 25 ; (19.2Kb/s at 8MHz)
-  ldi r17, 0
-.endif
-
-.if clock == 1000000
-  ldi r16, 3  ; (19.2Kb/s at 1MHz)
-  ldi r17, 0  
-.endif
-
-  sts UBRR1H, r17
-  sts UBRR1L, r16
-
-  ; set character format (asynchronous USART, 8-bit, one stop bit, no parity)
-  ldi r16, (3<<UCSZ10)
-  sts UCSR1C, r16
-
-  ; enable transceiver
-  lds r16, UCSR1B
-;  cbr r16, (1<<UDRIE1)  ; disable DRE interrupt
-  ori r16, (1<<RXEN1) | (1<<TXEN1)   ; enable transmit and receive
-  sts UCSR1B, r16
-
-.ifdef COM_ATTN_PUE
-    lds r16, COM_ATTN_PUE
-    cbr r16, COM_ATTN_PIN           ; disable pullup on ATTN
-    sts COM_ATTN_PUE, r16
-.endif
-
-  ret
-;@end
-
-
-
-; ---------------------------------------------------------------------------
-; @routine ioRawSendMsg
-; Send a message
-;
-; @clobbers r16, r17, X
-
-ioRawSendMsg:
-  ldi xl, LOW(flashSendBuffer)
-  ldi xh, HIGH(flashSendBuffer)
-  rjmp ioRawSendPacket          ; (r16, r17, X)
-; @end
-
-
-
-; ---------------------------------------------------------------------------
-; @routine UART_HW_Uart1_RawSendPacket
-; Send packet.
-;
-; @param X buffer to send
-; @return CFLAG: set if okay (packet sent), cleared on error
-; @clobbers r16, r17, X
-
-ioRawSendPacket:
-  adiw xh:xl, 1
-  ld r17, X
-  sbiw xh:xl, 1
-  ldi r16, 3                     ; add DEST, LEN, CRC bytes
-  add r17, r16
-ioRawSendPacket_loop:
-      lds r16, UCSR1A
-      sbrs r16, UDRE1
-    rjmp ioRawSendPacket_loop
-    sbr r16, (1<<TXC1)
-    sts UCSR1A, r16
-    ld r16, X+
-    sts UDR1, r16
-    dec r17
-  brne ioRawSendPacket_loop
-  sec
-  ret
-; @end
-
-
-
-
-
-
-; ---------------------------------------------------------------------------
-; @routine ioRawWaitForValidMsg
-; Wait for valid incoming msg
-;
-; @return CFLAG set if okay (packet received), cleared on error
-; @clobbers: r16, r17, r18 (r19, r22, X)
-
-ioRawWaitForValidMsg:
-  ldi xl, LOW(flashRecvBuffer)
-  ldi xh, HIGH(flashRecvBuffer)
-  ldi r18, FLASH_RECVBUFFER_MAXLEN-3  ; maximum accepted msglen byte
-  ldi r20, 10                         ; 10 secs
-  rjmp ioRecvMsg
-; @end
-
-
-
-; ---------------------------------------------------------------------------
-; @routine ioRecvMsg
-;
-; Wait for next message, if received check validity.
-; On error skip the currently received message.
-;
-; @return CFLAG set if okay, cleared on error
-; @param  r18   max accepted msglen size (buffersize-3)
-; @param  R20   max number of secs to wait for incoming message
-; @param  X     buffer to receive to
-; @clobbers (r16, r17, r18, r19, r20, r22)
-
-ioRecvMsg:
-  rcall ioRawRecvMsg                      ; (r16, r17, r18, r19, r20, r22)
-  brcc ioRecvMsg_error
-  push xl
-    push xh
-      rcall NETMSG_CheckMessageInBuffer   ; (R16, R17, R18, R19, R20, X)
-    pop xh
-  pop xl
-  brcs ioRecvMsg_end
-ioRecvMsg_error:
-  rcall ioRecvSkipMessage                 ; skip remainder of the message
-  clc
-ioRecvMsg_end:
-  ret
-; @end
-
-
-
-; ---------------------------------------------------------------------------
-; @routine ioRecvSkipMessage
-;
-; skip all receiption data until a data pause of about 10ms
-;
-; @clobbers r16
-
-ioRecvSkipMessage:
-ioRecvSkipMessage_loop:
-    rcall ioRecvFlush               ; (r16)
-    ; wait for a data pause of 10ms
-    rcall ioRawRecvByteWithin10ms   ; (r20, r22)
-  brcs ioRecvSkipMessage_loop
-  ret
-; @end
-
-
-
-; ---------------------------------------------------------------------------
-; @routine ioRecvFlush
-;
-; flush receiption buffer.
-;
-; @clobbers r16
-
-ioRecvFlush:
-    lds r16, UCSR1A ; read status
-    sbrs r16, RXC1
-    ret
-    lds r16, UDR1   ; read data byte
-  rjmp ioRecvFlush
-; @end
-
-
-
-; ---------------------------------------------------------------------------
-; @routine ioRawRecvMsg
-;
-; @return   CFLAG set if okay, cleared on error
-; @param    r18   max accepted msglen size (buffersize-3)
-; @param    R20   max number of secs to wait for incoming message
-; @param    X     buffer to receive to
-; @clobbers r16, r17, r19 (r18, r20, r22)
-
-ioRawRecvMsg:
-  lds r19, UCSR1A
-  cbr r19, (1<<FE1) | (1<<DOR1) | (1<<UPE1)
-  sts UCSR1A, r19               ; clear errors
-  ; wait for begin of message
-  rcall ioRawWaitForDataSeconds ; (r20, r22)
-  brcc ioRawRecvMsg_end
-  clr r19                       ; bytecounter
-  ; read first two bytes
-  ldi r17, 2                    ; 2 bytes: address byte, msg len
-  add r19, r17
-  rcall ioRawRecvBytes          ; (r16, r17, r18, r22)
-  brcc ioRawRecvMsg_error
-  cp r16, r20                   ; check size
-  brcc ioRawRecvMsg_error
-  inc r16                       ; account for checksum byte
-  ; read remaining bytes including checksum byte
-  mov r17, r16
-  add r19, r17
-  rcall ioRawRecvBytes          ; (r16, r17, r18, r22)
-  brcc ioRawRecvMsg_error
-  sub xl, r19                   ; let X point back to begin of message
-  sbc xh, r19
-  add xh, r19
-  sec
-  ret
-ioRawRecvMsg_error:
-  clc
-ioRawRecvMsg_end:
-  ret
-; @end
-
-
-
-; ---------------------------------------------------------------------------
-; @routine ioRawRecvBytes
-;
-; @return CFLAG set if okay (data available), cleared on error
-; @return r16 last byte received
-; @param r17 number of bytes to read
-; @param x buffer to receive to
-; @clobbers r16, r17 (r20, r22)
-
-ioRawRecvBytes:
-    rcall ioRawRecvByteWithin10ms ; (r20, r22)
-    brcc ioRawRecvBytes_end
-    st X+, r16
-    dec r17
-  brne ioRawRecvBytes
-  sec
-ioRawRecvBytes_end:
-  ret
-; @end
-
-
-
-; ---------------------------------------------------------------------------
-; @routine ioRawRecvByteWithin10ms
-;
-; Wait up to 10ms for incoming byte and read it.
-;
-; @return CFLAG set if okay (data available), cleared on error
-; @return r16 byte received (if CFLAG set)
-; @clobbers: r20, r22
-
-ioRawRecvByteWithin10ms:
-  rcall ioRawWaitForData10ms                   ; (R20, R22)
-  brcc ioRawRecvByteWithin10ms_end
-  lds r16, UCSR1A                              ; check for errors
-  andi r16, (1<<FE1) | (1<<DOR1) | (1<<UPE1)
-  brne ioRawRecvByteWithin10ms_error
-  lds r16, UDR1                                ; read data byte
-  sec
-  ret
-ioRawRecvByteWithin10ms_error:
-  clc
-ioRawRecvByteWithin10ms_end:
-  ret
-; @end
-
-
-
-; ---------------------------------------------------------------------------
-; @routine ioRawWaitForDataSeconds
-;
-; Wait for incoming data for max 1s
-;
-; @return CFLAG set if okay (data available), cleared on error
-; @param r20 maximum number of seconds to wait
-; @clobbers: r20, r22
-
-ioRawWaitForDataSeconds:
-ioRawWaitForDataSeconds_loop:
-    push r20
-      rcall ioRawWaitForData1s              ; (r20, r22)
-    pop r20
-    brcs ioRawWaitForDataSeconds_gotit
-    sbi LED_PIN, LED_PINNUM                 ; toggle
-    dec r20
-  brne ioRawWaitForDataSeconds_loop
-  clc
-ioRawWaitForDataSeconds_gotit:
-  ret
-; @end
-
-
-
-; ---------------------------------------------------------------------------
-; @routine ioRawWaitForData1s
-;
-; Wait for incoming data for max 1s
-;
-; @return CFLAG set if okay (data available), cleared on error
-; @clobbers: r20, r22
-
-ioRawWaitForData1s:
-  ldi r20, 100
-ioRawWaitForData1s_loop:
-    push r20
-      rcall ioRawWaitForData10ms   ; (R20, R22)
-    pop r20
-    brcs ioRawWaitForData1s_gotit
-    dec r20
-  brne ioRawWaitForData1s_loop
-  clc
-ioRawWaitForData1s_gotit:
-  ret
-; @end
-
-
-
-; ---------------------------------------------------------------------------
-; @routine ioRawWaitForData10ms
-;
-; Wait for incoming data for max 10 milliseconds.
-;
-; @return CFLAG set if okay (data available), cleared on error
-; @clobbers: r20, r22
-
-ioRawWaitForData10ms:
-.if clock == 8000000
-  ldi r20, 80
-.endif
-.if clock == 1000000
-  ldi r20, 10
-.endif
-ioRawWaitForData10ms_loop:
-    push r20
-      rcall ioRawWaitForData1000Cycles  ; (r20, r22)
-    pop r20
-    brcs ioRawWaitForData10ms_gotit
-    dec r20
-  brne ioRawWaitForData10ms_loop
-  clc
-ioRawWaitForData10ms_gotit:
-  ret
-; @end
-
-
-
-; ---------------------------------------------------------------------------
-; @routine ioRawWaitForData1000Cycles
-;
-; Wait for incoming data for max 1000 clock cycles
-; (about 1ms at 1MHz, 0.125 at 8MHz)
-;
-; @return CFLAG set if okay (packet received), cleared on error
-; @clobbers: r20, r22
-
-ioRawWaitForData1000Cycles:
-  ldi r20, 140                         ; 1
-ioRawWaitForData_loop:
-    lds r22, UCSR1A                    ; 2
-    sbrc r22, RXC1                     ; 2/3
-      rjmp ioRawWaitForData_gotit      ; 2
-    dec r20                            ; 1
-  brne ioRawWaitForData_loop           ; 1/2  -> 7 per loop, max about 1000
-  clc                                  ; 1
-  ret                                  ; 4
-ioRawWaitForData_gotit:
-  sec                                  ; 1
-  ret                                  ; 4
-; @end
+.equ  UART_REG_UDR   = UDR1
+.equ  UART_REG_UCSRA = UCSR1A
+.equ  UART_REG_UCSRB = UCSR1B
+.equ  UART_REG_UCSRC = UCSR1C
+.equ  UART_REG_UBRRL = UBRR1L
+.equ  UART_REG_UBRRH = UBRR1H
+
+.equ  UART_BIT_UCSZ0 = UCSZ10
+.equ  UART_BIT_UDRE  = UDRE1
+.equ  UART_BIT_RXC   = RXC1
+.equ  UART_BIT_TXC   = TXC1
+.equ  UART_BIT_FE    = FE1
+.equ  UART_BIT_DOR   = DOR1
+.equ  UART_BIT_UPE   = UPE1
+.equ  UART_BIT_RXEN  = RXEN1
+.equ  UART_BIT_TXEN  = TXEN1
 
 
 
diff --git a/avr/modules/flash/io_uart_all.asm b/avr/modules/flash/io_uart_all.asm
new file mode 100644
index 0000000..118d900
--- /dev/null
+++ b/avr/modules/flash/io_uart_all.asm
@@ -0,0 +1,387 @@
+; ***************************************************************************
+; copyright   : (C) 2025 by Martin Preuss
+; email       : martin@libchipcard.de
+;
+; ***************************************************************************
+; * This file is part of the project "AqHome".                              *
+; * Please see toplevel file COPYING of that project for license details.   *
+; ***************************************************************************
+
+
+; ***************************************************************************
+; code
+
+
+.cseg
+
+
+; ---------------------------------------------------------------------------
+; @routine ioRawInit
+; Send a message
+;
+; @clobbers r16, r17
+
+ioRawInit:
+  ; set baudrate
+.if clock == 8000000
+  ldi r16, 25 ; (19.2Kb/s at 8MHz)
+  ldi r17, 0
+.endif
+
+.if clock == 1000000
+  ldi r16, 3  ; (19.2Kb/s at 1MHz)
+  ldi r17, 0  
+.endif
+
+  sts UART_REG_UBRRH, r17
+  sts UART_REG_UBRRL, r16
+
+  ; set character format (asynchronous USART, 8-bit, one stop bit, no parity)
+  ldi r16, (3<<UART_BIT_UCSZ0)
+  sts UART_REG_UCSRC, r16
+
+  ; enable transceiver
+  lds r16, UART_REG_UCSRB
+;  cbr r16, (1<<UDRIE1)  ; disable DRE interrupt
+  ori r16, (1<<UART_BIT_RXEN) | (1<<UART_BIT_TXEN)   ; enable transmit and receive
+  sts UART_REG_UCSRB, r16
+
+.ifdef COM_ATTN_PUE
+    lds r16, COM_ATTN_PUE
+    cbr r16, COM_ATTN_PIN             ; disable pullup on ATTN
+    sts COM_ATTN_PUE, r16
+.else
+    cbi COM_ATTN_OUTPUT, COM_ATTN_PIN ; disable internal pullup for ATTN
+
+.endif
+
+  ret
+;@end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine ioRawSendMsg
+; Send a message
+;
+; @clobbers r16, r17, X
+
+ioRawSendMsg:
+  ldi xl, LOW(flashSendBuffer)
+  ldi xh, HIGH(flashSendBuffer)
+  rjmp ioRawSendPacket          ; (r16, r17, X)
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine UART_HW_Uart1_RawSendPacket
+; Send packet.
+;
+; @param X buffer to send
+; @return CFLAG: set if okay (packet sent), cleared on error
+; @clobbers r16, r17, X
+
+ioRawSendPacket:
+  adiw xh:xl, 1
+  ld r17, X
+  sbiw xh:xl, 1
+  ldi r16, 3                     ; add DEST, LEN, CRC bytes
+  add r17, r16
+ioRawSendPacket_loop:
+      lds r16, UART_REG_UCSRA
+      sbrs r16, UART_BIT_UDRE
+    rjmp ioRawSendPacket_loop
+    sbr r16, (1<<UART_BIT_TXC)
+    sts UART_REG_UCSRA, r16
+    ld r16, X+
+    sts UART_REG_UDR, r16
+    dec r17
+  brne ioRawSendPacket_loop
+  sec
+  ret
+; @end
+
+
+
+
+
+
+; ---------------------------------------------------------------------------
+; @routine ioRawWaitForValidMsg
+; Wait for valid incoming msg
+;
+; @return CFLAG set if okay (packet received), cleared on error
+; @clobbers: r16, r17, r18 (r19, r22, X)
+
+ioRawWaitForValidMsg:
+  ldi xl, LOW(flashRecvBuffer)
+  ldi xh, HIGH(flashRecvBuffer)
+  ldi r18, FLASH_RECVBUFFER_MAXLEN-3  ; maximum accepted msglen byte
+  ldi r20, 10                         ; 10 secs
+  rjmp ioRecvMsg
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine ioRecvMsg
+;
+; Wait for next message, if received check validity.
+; On error skip the currently received message.
+;
+; @return CFLAG set if okay, cleared on error
+; @param  r18   max accepted msglen size (buffersize-3)
+; @param  R20   max number of secs to wait for incoming message
+; @param  X     buffer to receive to
+; @clobbers (r16, r17, r18, r19, r20, r22)
+
+ioRecvMsg:
+  rcall ioRawRecvMsg                      ; (r16, r17, r18, r19, r20, r22)
+  brcc ioRecvMsg_error
+  push xl
+    push xh
+      rcall NETMSG_CheckMessageInBuffer   ; (R16, R17, R18, R19, R20, X)
+    pop xh
+  pop xl
+  brcs ioRecvMsg_end
+ioRecvMsg_error:
+  rcall ioRecvSkipMessage                 ; skip remainder of the message
+  clc
+ioRecvMsg_end:
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine ioRecvSkipMessage
+;
+; skip all receiption data until a data pause of about 10ms
+;
+; @clobbers r16
+
+ioRecvSkipMessage:
+ioRecvSkipMessage_loop:
+    rcall ioRecvFlush               ; (r16)
+    ; wait for a data pause of 10ms
+    rcall ioRawRecvByteWithin10ms   ; (r20, r22)
+  brcs ioRecvSkipMessage_loop
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine ioRecvFlush
+;
+; flush receiption buffer.
+;
+; @clobbers r16
+
+ioRecvFlush:
+    lds r16, UART_REG_UCSRA ; read status
+    sbrs r16, UART_BIT_RXC
+    ret
+    lds r16, UART_REG_UDR   ; read data byte
+  rjmp ioRecvFlush
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine ioRawRecvMsg
+;
+; @return   CFLAG set if okay, cleared on error
+; @param    r18   max accepted msglen size (buffersize-3)
+; @param    R20   max number of secs to wait for incoming message
+; @param    X     buffer to receive to
+; @clobbers r16, r17, r19 (r18, r20, r22)
+
+ioRawRecvMsg:
+  lds r19, UART_REG_UCSRA
+  cbr r19, (1<<UART_BIT_FE) | (1<<UART_BIT_DOR) | (1<<UART_BIT_UPE)
+  sts UART_REG_UCSRA, r19               ; clear errors
+  ; wait for begin of message
+  rcall ioRawWaitForDataSeconds ; (r20, r22)
+  brcc ioRawRecvMsg_end
+  clr r19                       ; bytecounter
+  ; read first two bytes
+  ldi r17, 2                    ; 2 bytes: address byte, msg len
+  add r19, r17
+  rcall ioRawRecvBytes          ; (r16, r17, r18, r22)
+  brcc ioRawRecvMsg_error
+  cp r16, r20                   ; check size
+  brcc ioRawRecvMsg_error
+  inc r16                       ; account for checksum byte
+  ; read remaining bytes including checksum byte
+  mov r17, r16
+  add r19, r17
+  rcall ioRawRecvBytes          ; (r16, r17, r18, r22)
+  brcc ioRawRecvMsg_error
+  sub xl, r19                   ; let X point back to begin of message
+  sbc xh, r19
+  add xh, r19
+  sec
+  ret
+ioRawRecvMsg_error:
+  clc
+ioRawRecvMsg_end:
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine ioRawRecvBytes
+;
+; @return CFLAG set if okay (data available), cleared on error
+; @return r16 last byte received
+; @param r17 number of bytes to read
+; @param x buffer to receive to
+; @clobbers r16, r17 (r20, r22)
+
+ioRawRecvBytes:
+    rcall ioRawRecvByteWithin10ms ; (r20, r22)
+    brcc ioRawRecvBytes_end
+    st X+, r16
+    dec r17
+  brne ioRawRecvBytes
+  sec
+ioRawRecvBytes_end:
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine ioRawRecvByteWithin10ms
+;
+; Wait up to 10ms for incoming byte and read it.
+;
+; @return CFLAG set if okay (data available), cleared on error
+; @return r16 byte received (if CFLAG set)
+; @clobbers: r20, r22
+
+ioRawRecvByteWithin10ms:
+  rcall ioRawWaitForData10ms                   ; (R20, R22)
+  brcc ioRawRecvByteWithin10ms_end
+  lds r16, UART_REG_UCSRA                           ; check for errors
+  andi r16, (1<<UART_BIT_FE) | (1<<UART_BIT_DOR) | (1<<UART_BIT_UPE)
+  brne ioRawRecvByteWithin10ms_error
+  lds r16, UART_REG_UDR                             ; read data byte
+  sec
+  ret
+ioRawRecvByteWithin10ms_error:
+  clc
+ioRawRecvByteWithin10ms_end:
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine ioRawWaitForDataSeconds
+;
+; Wait for incoming data for max 1s
+;
+; @return CFLAG set if okay (data available), cleared on error
+; @param r20 maximum number of seconds to wait
+; @clobbers: r20, r22
+
+ioRawWaitForDataSeconds:
+ioRawWaitForDataSeconds_loop:
+    push r20
+      rcall ioRawWaitForData1s              ; (r20, r22)
+    pop r20
+    brcs ioRawWaitForDataSeconds_gotit
+    sbi LED_PIN, LED_PINNUM                 ; toggle
+    dec r20
+  brne ioRawWaitForDataSeconds_loop
+  clc
+ioRawWaitForDataSeconds_gotit:
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine ioRawWaitForData1s
+;
+; Wait for incoming data for max 1s
+;
+; @return CFLAG set if okay (data available), cleared on error
+; @clobbers: r20, r22
+
+ioRawWaitForData1s:
+  ldi r20, 100
+ioRawWaitForData1s_loop:
+    push r20
+      rcall ioRawWaitForData10ms   ; (R20, R22)
+    pop r20
+    brcs ioRawWaitForData1s_gotit
+    dec r20
+  brne ioRawWaitForData1s_loop
+  clc
+ioRawWaitForData1s_gotit:
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine ioRawWaitForData10ms
+;
+; Wait for incoming data for max 10 milliseconds.
+;
+; @return CFLAG set if okay (data available), cleared on error
+; @clobbers: r20, r22
+
+ioRawWaitForData10ms:
+.if clock == 8000000
+  ldi r20, 80
+.endif
+.if clock == 1000000
+  ldi r20, 10
+.endif
+ioRawWaitForData10ms_loop:
+    push r20
+      rcall ioRawWaitForData1000Cycles  ; (r20, r22)
+    pop r20
+    brcs ioRawWaitForData10ms_gotit
+    dec r20
+  brne ioRawWaitForData10ms_loop
+  clc
+ioRawWaitForData10ms_gotit:
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine ioRawWaitForData1000Cycles
+;
+; Wait for incoming data for max 1000 clock cycles
+; (about 1ms at 1MHz, 0.125 at 8MHz)
+;
+; @return CFLAG set if okay (packet received), cleared on error
+; @clobbers: r20, r22
+
+ioRawWaitForData1000Cycles:
+  ldi r20, 140                         ; 1
+ioRawWaitForData_loop:
+    lds r22, UART_REG_UCSRA            ; 2
+    sbrc r22, UART_BIT_RXC             ; 2/3
+      rjmp ioRawWaitForData_gotit      ; 2
+    dec r20                            ; 1
+  brne ioRawWaitForData_loop           ; 1/2  -> 7 per loop, max about 1000
+  clc                                  ; 1
+  ret                                  ; 4
+ioRawWaitForData_gotit:
+  sec                                  ; 1
+  ret                                  ; 4
+; @end
+
+
+
+
diff --git a/avr/modules/flash/io_uart_all_attn.asm b/avr/modules/flash/io_uart_all_attn.asm
new file mode 100644
index 0000000..c503229
--- /dev/null
+++ b/avr/modules/flash/io_uart_all_attn.asm
@@ -0,0 +1,495 @@
+; ***************************************************************************
+; copyright   : (C) 2025 by Martin Preuss
+; email       : martin@libchipcard.de
+;
+; ***************************************************************************
+; * This file is part of the project "AqHome".                              *
+; * Please see toplevel file COPYING of that project for license details.   *
+; ***************************************************************************
+
+
+; ***************************************************************************
+; code
+
+
+.cseg
+
+
+; ---------------------------------------------------------------------------
+; @routine ioRawInit
+; Send a message
+;
+; @clobbers r16, r17
+
+ioRawInit:
+  ; set baudrate
+.if clock == 8000000
+  ldi r16, 25 ; (19.2Kb/s at 8MHz)
+  ldi r17, 0
+.endif
+
+.if clock == 1000000
+  ldi r16, 3  ; (19.2Kb/s at 1MHz)
+  ldi r17, 0  
+.endif
+
+  M_IO_WRITE UART_REG_UBRRH, r17
+  M_IO_WRITE UART_REG_UBRRL, r16
+
+  ; set character format (asynchronous USART, 8-bit, one stop bit, no parity)
+  ldi r16, (1<<UART_BIT_UCSZ0) | (1<<UART_BIT_UCSZ1)
+  sts UART_REG_UCSRC, r16
+
+  cbi COM_ATTN_DDR, COM_ATTN_PIN          ; set ATTN port as input
+
+.ifdef COM_ATTN_PUE
+    lds r16, COM_ATTN_PUE
+    cbr r16, COM_ATTN_PIN             ; disable pullup on ATTN
+    sts COM_ATTN_PUE, r16
+.else
+    cbi COM_ATTN_OUTPUT, COM_ATTN_PIN ; disable internal pullup for ATTN
+.endif
+
+  ret
+;@end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine ioRawSendMsg
+; Send a message
+;
+; @clobbers r16, r17, X
+
+ioRawSendMsg:
+    ldi xl, LOW(flashSendBuffer)
+    ldi xh, HIGH(flashSendBuffer)
+    rcall ioRawSendMsgWithAttn
+  brcc ioRawSendMsg
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine ioRawSendMsgWithAttn
+;
+; @param X buffer to send
+; @return CFLAG: set if okay (packet sent), cleared on error
+; @clobbers r16, r17 (X)
+
+ioRawSendMsgWithAttn:
+ioRawSendMsgWithAttn_loop:
+    ldi r16, 0xff                        ; expect ATTN high
+    ldi r17, 10
+    rcall ioWaitForAttnState100ms        ; wait for up to 1s
+    brcs ioRawSendMsgWithAttn_attnHigh
+    ret
+ioRawSendMsgWithAttn_attnHigh:
+    rcall ioRawAcquireBus                ; (none)
+  brcc ioRawSendMsgWithAttn_loop
+
+  rcall ioRawWaitForOneBitLength         ; wait for one bit duration (R22)
+  rcall ioRawWaitForOneBitLength         ; wait for one bit duration (R22)
+
+  rcall ioRawSendMsgHandleTransceiver    ; (r16, r17, X)
+  cbi COM_ATTN_DDR, COM_ATTN_PIN         ; release ATTN line (by setting direction to IN)
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine ioRawSendMsgHandleTransceiver
+; Enable transceiver, send packet, disable transceiver.
+;
+; @param X buffer to send
+; @return CFLAG: set if okay (packet sent), cleared on error
+; @clobbers r16 (r17, X)
+
+ioRawSendMsgHandleTransceiver:
+  ; enable transceiver
+  M_IO_READ r16, UART_REG_UCSRB
+  sbr r16,(1<<UART_BIT_TXEN)           ; enable transmit
+  M_IO_WRITE UART_REG_UCSRB, r16
+  rcall ioRawSendMsgDirect
+  ; disable transceiver
+  M_IO_READ r16, UART_REG_UCSRB
+  cbr r16,(1<<UART_BIT_TXEN)           ; disable transmit
+  M_IO_WRITE UART_REG_UCSRB, r16
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine ioRawSendMsgDirect
+; Send packet.
+;
+; @param X buffer to send
+; @return CFLAG: set if okay (packet sent), cleared on error
+; @clobbers r16, r17, X
+
+ioRawSendMsgDirect:
+  adiw xh:xl, 1
+  ld r17, X                      ; read msg size
+  sbiw xh:xl, 1
+  ldi r16, 3                     ; add DEST, LEN, CRC bytes
+  add r17, r16
+ioRawSendMsgDirect_loop:
+    ; wait until transceiver ready
+      M_IO_READ r16, UART_REG_UCSRA
+      sbrs r16, UART_BIT_UDRE
+    rjmp ioRawSendMsgDirect_loop
+    ; clear TXC flag by sending a 1
+    sbr r16, (1<<UART_BIT_TXC)
+    M_IO_WRITE UART_REG_UCSRA, r16
+    ; write byte to uart data register
+    ld r16, X+
+    M_IO_WRITE UART_REG_UDR, r16
+    dec r17
+  brne ioRawSendMsgDirect_loop
+  ; wait until all data send (i.e. send buffer empty and all bits shifted out)
+ioRawSendMsgDirect_loopComplete:
+    M_IO_READ r16, UART_REG_UCSRA
+    sbrs r16, UART_BIT_TXC
+  rjmp ioRawSendMsgDirect_loopComplete
+  sec
+  ret
+; @end
+
+
+
+
+
+
+; ---------------------------------------------------------------------------
+; @routine ioRawWaitForValidMsg
+; Wait for valid incoming msg
+;
+; @return CFLAG set if okay (packet received), cleared on error
+; @clobbers: r16, r17, r18 (r19, r22, X)
+
+ioRawWaitForValidMsg:
+  ldi r16, 0xff                         ; expect ATTN high
+  ldi r17, 100
+  rcall ioWaitForAttnState100ms         ; wait for up to 10s
+  brcc ioRawWaitForValidMsg_end         ; ATTN not high, exit
+  ldi r16, 0                            ; expect ATTN low
+  ldi r17, 100
+  rcall ioWaitForAttnState100ms         ; wait for up to 10s
+  brcs ioRawWaitForValidMsg_attnLow
+  ret
+ioRawWaitForValidMsg_attnLow:
+  ldi xl, LOW(flashRecvBuffer)
+  ldi xh, HIGH(flashRecvBuffer)
+  ldi r18, FLASH_RECVBUFFER_MAXLEN-3    ; maximum accepted msglen byte
+  ldi r20, 10                           ; 10 secs
+  rcall ioRecvMsgHandleReceiver         ; (r16, r17, r18, r19, r20, r22)
+  brcs ioRawWaitForValidMsg_packetReceived
+  ; wait until ATTN is high (up to 10s)
+  ldi r16, 0xff                         ; expect ATTN high
+  ldi r17, 100
+  rcall ioWaitForAttnState100ms         ; wait for up to 10s
+  clc
+  ret
+ioRawWaitForValidMsg_packetReceived:
+  ldi r16, 0xff                         ; expect ATTN high
+  ldi r17, 100
+  rcall ioWaitForAttnState100ms         ; wait for up to 10s
+  brcc ioRawWaitForValidMsg_end
+  ldi xl, LOW(flashRecvBuffer)
+  ldi xh, HIGH(flashRecvBuffer)
+  rcall NETMSG_CheckMessageInBuffer
+ioRawWaitForValidMsg_end:
+  ret
+
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine ioRecvMsgHandleReceiver
+;
+; Turn receiver on, receive message, turn receiver off.
+; @return CFLAG set if okay, cleared on error
+; @param  r18   max accepted msglen size (buffersize-3)
+; @param  R20   max number of secs to wait for incoming message
+; @param  X     buffer to receive to
+; @clobbers r16 (r17, r18, r19, r20, r22)
+
+ioRecvMsgHandleReceiver:
+  ; enable receiver
+  M_IO_READ r16, UART_REG_UCSRB
+  sbr r16,(1<<UART_BIT_RXEN)           ; enable receive
+  M_IO_WRITE UART_REG_UCSRB, r16
+  rcall ioRecvMsg
+  M_IO_READ r16, UART_REG_UCSRB
+  cbr r16,(1<<UART_BIT_RXEN)           ; disable receive
+  M_IO_WRITE UART_REG_UCSRB, r16
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine ioRecvMsg
+;
+; Wait for next message, if received check validity.
+; On error skip the currently received message.
+;
+; @return CFLAG set if okay, cleared on error
+; @param  r18   max accepted msglen size (buffersize-3)
+; @param  R20   max number of secs to wait for incoming message
+; @param  X     buffer to receive to
+; @clobbers (r16, r17, r18, r19, r20, r22)
+
+ioRecvMsg:
+  rcall ioRawRecvMsg                      ; (r16, r17, r18, r19, r20, r22)
+  brcc ioRecvMsg_error
+  push xl
+    push xh
+      rcall NETMSG_CheckMessageInBuffer   ; (R16, R17, R18, R19, R20, X)
+    pop xh
+  pop xl
+  brcs ioRecvMsg_end
+ioRecvMsg_error:
+  rcall ioRecvSkipMessage                 ; skip remainder of the message
+  clc
+ioRecvMsg_end:
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine ioRecvSkipMessage
+;
+; skip all receiption data until a data pause of about 10ms
+;
+; @clobbers r16
+
+ioRecvSkipMessage:
+ioRecvSkipMessage_loop:
+    rcall ioRecvFlush               ; (r16)
+    ; wait for a data pause of 10ms
+    rcall ioRawRecvByteWithin10ms   ; (r20, r22)
+  brcs ioRecvSkipMessage_loop
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine ioRecvFlush
+;
+; flush receiption buffer.
+;
+; @clobbers r16
+
+ioRecvFlush:
+    M_IO_READ r16, UART_REG_UCSRA ; read status
+    sbrs r16, UART_BIT_RXC
+    ret
+    M_IO_READ r16, UART_REG_UDR   ; read data byte
+  rjmp ioRecvFlush
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine ioRawRecvMsg
+;
+; @return   CFLAG set if okay, cleared on error
+; @param    r18   max accepted msglen size (buffersize-3)
+; @param    R20   max number of secs to wait for incoming message
+; @param    X     buffer to receive to
+; @clobbers r16, r17, r19 (r18, r20, r22)
+
+ioRawRecvMsg:
+  M_IO_READ r19, UART_REG_UCSRA
+  cbr r19, (1<<UART_BIT_FE) | (1<<UART_BIT_DOR) | (1<<UART_BIT_UPE)
+  M_IO_WRITE UART_REG_UCSRA, r19               ; clear errors
+  ; wait for begin of message
+  rcall ioRawWaitForDataSeconds ; (r20, r22)
+  brcc ioRawRecvMsg_end
+  clr r19                       ; bytecounter
+  ; read first two bytes
+  ldi r17, 2                    ; 2 bytes: address byte, msg len
+  add r19, r17
+  rcall ioRawRecvBytes          ; (r16, r17, r18, r22)
+  brcc ioRawRecvMsg_error
+  cp r16, r20                   ; check size
+  brcc ioRawRecvMsg_error
+  inc r16                       ; account for checksum byte
+  ; read remaining bytes including checksum byte
+  mov r17, r16
+  add r19, r17
+  rcall ioRawRecvBytes          ; (r16, r17, r18, r22)
+  brcc ioRawRecvMsg_error
+  sub xl, r19                   ; let X point back to begin of message
+  sbc xh, r19
+  add xh, r19
+  sec
+  ret
+ioRawRecvMsg_error:
+  clc
+ioRawRecvMsg_end:
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine ioRawRecvBytes
+;
+; @return CFLAG set if okay (data available), cleared on error
+; @return r16 last byte received
+; @param r17 number of bytes to read
+; @param x buffer to receive to
+; @clobbers r16, r17 (r20, r22)
+
+ioRawRecvBytes:
+    rcall ioRawRecvByteWithin10ms ; (r20, r22)
+    brcc ioRawRecvBytes_end
+    st X+, r16
+    dec r17
+  brne ioRawRecvBytes
+  sec
+ioRawRecvBytes_end:
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine ioRawRecvByteWithin10ms
+;
+; Wait up to 10ms for incoming byte and read it.
+;
+; @return CFLAG set if okay (data available), cleared on error
+; @return r16 byte received (if CFLAG set)
+; @clobbers: r20, r22
+
+ioRawRecvByteWithin10ms:
+  rcall ioRawWaitForData10ms                   ; (R20, R22)
+  brcc ioRawRecvByteWithin10ms_end
+  M_IO_READ r16, UART_REG_UCSRA                           ; check for errors
+  andi r16, (1<<UART_BIT_FE) | (1<<UART_BIT_DOR) | (1<<UART_BIT_UPE)
+  brne ioRawRecvByteWithin10ms_error
+  M_IO_READ r16, UART_REG_UDR                             ; read data byte
+  sec
+  ret
+ioRawRecvByteWithin10ms_error:
+  clc
+ioRawRecvByteWithin10ms_end:
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine ioRawWaitForDataSeconds
+;
+; Wait for incoming data for max 1s
+;
+; @return CFLAG set if okay (data available), cleared on error
+; @param r20 maximum number of seconds to wait
+; @clobbers: r20, r22
+
+ioRawWaitForDataSeconds:
+ioRawWaitForDataSeconds_loop:
+    push r20
+      rcall ioRawWaitForData1s              ; (r20, r22)
+    pop r20
+    brcs ioRawWaitForDataSeconds_gotit
+    sbi LED_PIN, LED_PINNUM                 ; toggle
+    dec r20
+  brne ioRawWaitForDataSeconds_loop
+  clc
+ioRawWaitForDataSeconds_gotit:
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine ioRawWaitForData1s
+;
+; Wait for incoming data for max 1s
+;
+; @return CFLAG set if okay (data available), cleared on error
+; @clobbers: r20, r22
+
+ioRawWaitForData1s:
+  ldi r20, 100
+ioRawWaitForData1s_loop:
+    push r20
+      rcall ioRawWaitForData10ms   ; (R20, R22)
+    pop r20
+    brcs ioRawWaitForData1s_gotit
+    dec r20
+  brne ioRawWaitForData1s_loop
+  clc
+ioRawWaitForData1s_gotit:
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine ioRawWaitForData10ms
+;
+; Wait for incoming data for max 10 milliseconds.
+;
+; @return CFLAG set if okay (data available), cleared on error
+; @clobbers: r20, r22
+
+ioRawWaitForData10ms:
+.if clock == 8000000
+  ldi r20, 80
+.endif
+.if clock == 1000000
+  ldi r20, 10
+.endif
+ioRawWaitForData10ms_loop:
+    push r20
+      rcall ioRawWaitForData1000Cycles  ; (r20, r22)
+    pop r20
+    brcs ioRawWaitForData10ms_gotit
+    dec r20
+  brne ioRawWaitForData10ms_loop
+  clc
+ioRawWaitForData10ms_gotit:
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine ioRawWaitForData1000Cycles
+;
+; Wait for incoming data for max 1000 clock cycles
+; (about 1ms at 1MHz, 0.125 at 8MHz)
+;
+; @return CFLAG set if okay (packet received), cleared on error
+; @clobbers: r20, r22
+
+ioRawWaitForData1000Cycles:
+  ldi r20, 140                         ; 1
+ioRawWaitForData_loop:
+    M_IO_READ r22, UART_REG_UCSRA      ; 2
+    sbrc r22, UART_BIT_RXC             ; 2/3
+      rjmp ioRawWaitForData_gotit      ; 2
+    dec r20                            ; 1
+  brne ioRawWaitForData_loop           ; 1/2  -> 7 per loop, max about 1000
+  clc                                  ; 1
+  ret                                  ; 4
+ioRawWaitForData_gotit:
+  sec                                  ; 1
+  ret                                  ; 4
+; @end
+
+
+
+
diff --git a/avr/modules/uart_hw/comonuart0.asm b/avr/modules/uart_hw/comonuart0.asm
index 60ebe7b..cc1e4ba 100644
--- a/avr/modules/uart_hw/comonuart0.asm
+++ b/avr/modules/uart_hw/comonuart0.asm
@@ -33,14 +33,19 @@ ComOnUart0_Init:
   rcall comOnUart0SetAttnInput   ; (none)
 
   rcall UART_HW_Interface_Init            ; (R16, R17, X)
-  rcall comOnUart0Init                ; (R16, R17, X)
+  rcall comOnUart0Init                    ; (R16, R17, X)
   ldi r16, COMONUART0_IFACENUM
   std Y+NET_IFACE_OFFS_IFACENUM, r16
 
-  sbi COM_IRQ_ADDR_ATTN, COM_IRQ_BIT_ATTN ; enable pin change irq for ATTN line
-  in r16, GIMSK                           ; enable pin change irq PCIE0 or PCIE1
-  ori r16, (1<<COM_IRQ_GIMSK_ATTN)
-  out GIMSK, R16
+  M_IO_READ r16, COM_IRQ_ADDR_ATTN        ; enable irq for ATTN line
+  sbr r16, COM_IRQ_BIT_ATTN
+  M_IO_WRITE COM_IRQ_ADDR_ATTN, r16
+
+.ifdef COM_IRQ_GIMSK_ATTN
+  M_IO_READ r16, GIMSK                    ; enable pin change irq PCIE0 or PCIE1
+  sbr r16, (1<<COM_IRQ_GIMSK_ATTN)
+  M_IO_WRITE GIMSK, R16
+.endif
   ldi r16, (1<<COM_IRQ_GIFR_ATTN)         ; clear pending irq by writing 1 to ATTN bit
   out GIFR, r16
 
diff --git a/avr/modules/uart_hw/m_lowlevel_uart.asm b/avr/modules/uart_hw/m_lowlevel_uart.asm
index d9da1b8..1985b1f 100644
--- a/avr/modules/uart_hw/m_lowlevel_uart.asm
+++ b/avr/modules/uart_hw/m_lowlevel_uart.asm
@@ -120,7 +120,7 @@ l_loop_%:
     lds r16, UCSR@0A
     sbrs r16, RXC@0
       rjmp l_end_%
-    lds r16, UDR@0
+    lds r16, USART@0_DATAREG
     clr r16
     std Y+NET_IFACE_OFFS_READTIMER, r16
   rjmp l_loop_%
@@ -146,7 +146,7 @@ l_end_%:
   lds r16, UCSR@0A
   sbrs r16, RXC@0
     rjmp l_end_%                                ; no data
-  lds r16, UDR@0                                ; r16=received char
+  lds r16, USART@0_DATAREG                                ; r16=received char
   ; check read mode
   ldd r17, Y+UART_HW_IFACE_OFFS_READMODE
   cpi r17, UART_HW_READMODE_READING
@@ -239,7 +239,7 @@ l_end_%:
   lds r16, UCSR@0A
   sbrs r16, RXC@0
     rjmp l_end_%                                ; no data
-  lds r16, UDR@0                                ; r16=received char
+  lds r16, USART@0_DATAREG                                ; r16=received char
   ; check read mode
   ldd r17, Y+UART_HW_IFACE_OFFS_READMODE
   cpi r17, UART_HW_READMODE_READING
@@ -355,7 +355,7 @@ l_end_%:
   std Y+UART_HW_IFACE_OFFS_WRITEBUFLEFT, r17
   
   ; send byte, reset write timer
-  sts UDR@0, r16
+  sts USART@0_DATAREG, r16
   clr r16
   std Y+NET_IFACE_OFFS_WRITETIMER, r16     ; reset write timer
   

From 484a455df76748efed0f8a820bb2ef01492cab7c Mon Sep 17 00:00:00 2001
From: Martin Preuss <martin@aquamaniac.de>
Date: Sat, 17 May 2025 10:51:04 +0200
Subject: [PATCH 12/13] t03: use new uart file.

---
 avr/devices/t03/boot/boot.asm | 1 +
 avr/devices/t03/defs.asm      | 5 +++++
 2 files changed, 6 insertions(+)

diff --git a/avr/devices/t03/boot/boot.asm b/avr/devices/t03/boot/boot.asm
index 1a83579..37a7147 100644
--- a/avr/devices/t03/boot/boot.asm
+++ b/avr/devices/t03/boot/boot.asm
@@ -131,6 +131,7 @@ main:
 .include "modules/flash/eeprom.asm"
 .include "modules/flash/io.asm"
 .include "modules/flash/io_uart1.asm"
+.include "modules/flash/io_uart_all.asm"
 .include "modules/flash/flashxp.asm"
 .include "modules/flash/flash4p.asm"
 .include "modules/flash/flashprocess.asm"
diff --git a/avr/devices/t03/defs.asm b/avr/devices/t03/defs.asm
index 2b6374a..75a19f4 100644
--- a/avr/devices/t03/defs.asm
+++ b/avr/devices/t03/defs.asm
@@ -77,4 +77,9 @@
 .equ OWI_PINNUM  = PORTA7
 
 
+; ---------------------------------------------------------------------------
+; ComOnUart module
+
+.equ  USART0_DATAREG   = UDR0
+.equ  USART1_DATAREG   = UDR1
 

From f8d3d097169ee1afe94253601805e3ebe32b2940 Mon Sep 17 00:00:00 2001
From: Martin Preuss <martin@aquamaniac.de>
Date: Sat, 17 May 2025 10:51:21 +0200
Subject: [PATCH 13/13] n21: fixed README.

---
 avr/devices/n21/README | 1 +
 1 file changed, 1 insertion(+)

diff --git a/avr/devices/n21/README b/avr/devices/n21/README
index 98c2591..55a3d2c 100644
--- a/avr/devices/n21/README
+++ b/avr/devices/n21/README
@@ -5,6 +5,7 @@ N21
 - Role: Door sensor with temp and motion detection
 - MCU: AtTiny84
 - Connection: RJ45
+- Predecessor: N16
 - Periphery:
   - PIR sensor (AMN31112)
   - door sensor (TCRT1000)