uart_hw2: basically works, but skips messages.

This commit is contained in:
Martin Preuss
2025-07-06 12:21:41 +02:00
parent fc5394a5c9
commit f930b846c2
5 changed files with 791 additions and 19 deletions

View File

@@ -27,6 +27,9 @@ comOnUart1_iface: .byte UART_HW2_IFACE_SIZE
; @clobbers R16, R17, Y (X)
ComOnUart1_Init:
rcall comOnUart1StopRx
rcall comOnUart1StopTx
ldi yl, LOW(comOnUart1_iface)
ldi yh, HIGH(comOnUart1_iface)
rcall NET_Interface_Init ; (R16, R17, X)
@@ -36,13 +39,23 @@ ComOnUart1_Init:
std Y+UART_HW2_IFACE_OFFS_MODE, r16
clr r16
std Y+NET_IFACE_OFFS_IFACENUM, r16
rcall comOnUart1SetAttnInput
sbi COM_IRQ_ADDR_ATTN1, COM_IRQ_BIT_ATTN1 ; enable pin change irq for ATTN line
inr r16, GIMSK ; enable pin change irq PCIE0 or PCIE1
.ifdef COM_ATTN1_PUE
inr r16, COM_ATTN1_PUE
cbr r16, (1<<COM_ATTN1_PIN)
outr COM_ATTN1_PUE, r16
.endif
inr r16, COM_IRQ_ADDR_ATTN1
sbr r16, (1<<COM_IRQ_BIT_ATTN1) ; enable pin change irq for ATTN line
outr COM_IRQ_ADDR_ATTN1, r16
inr r16, GIMSK ; enable pin change irq PCIE0 or PCIE1
sbr r16, (1<<COM_IRQ_GIMSK_ATTN1)
outr GIMSK, r16
ldi r16, (1<<COM_IRQ_GIFR_ATTN1) ; clear pending irq by writing 1 to ATTN bit
ldi r16, (1<<COM_IRQ_GIFR_ATTN1) ; clear pending irq by writing 1 to ATTN bit
outr GIFR, r16
; set baudrate
@@ -210,6 +223,14 @@ comOnUart1StartWriting_end:
; @clobbers all
ComOnUart1_Run:
push r15
inr r15, SREG
cli
rcall ComOnUart1_Run_noirq
outr SREG, r15
pop r15
ret
ComOnUart1_Run_noirq:
ldi yl, LOW(comOnUart1_iface)
ldi yh, HIGH(comOnUart1_iface)
ldd r16, Y+UART_HW2_IFACE_OFFS_MODE
@@ -323,7 +344,7 @@ comOnUart1RunMsgReceived:
brcc comOnUart1RunMsgReceived_enobuf
mov r18, r16 ; buffer num
rcall NET_Interface_SetIfaceNumInBuffer ; (R16, R17)
adiw xh:xl, 1
adiw xh:xl, 1 ; skip buffer header
ldd r17, Y+UART_HW2_IFACE_OFFS_BUFUSED ; always is at least 2 here
comOnUart1RunMsgReceived_copyLoop:
ld r16, Z+
@@ -396,7 +417,7 @@ comOnUart1RunMsgSent:
ldi r16, UART_HW2_MODE_IDLE
rcall comOnUart1SetMode ; (R17)
rcall comOnUart1SetAttnInput ; release ATTN (none)
rcall Utils_WaitFor10MicroSecs ; make sure ATTN is at least for a short period high (R22)
rcall Utils_WaitFor10MicroSecs ; make sure ATTN is at least high for a short period (R22)
ret
; @end
@@ -463,11 +484,11 @@ comOnUart1StopRx:
; @clobbers R16
comOnUart1StartTx:
lds r16, UCSR1A
inr r16, UCSR1A
cbr r16, (1<<TXC1) ; clear TXCn interrupt
outr UCSR1A, r16
inr r16, UCSR1B
sbr r16, (1<<UDRIE1) | (1<<TXCIE1) | (1<<TXEN1) ; enable TX UDRE and TXC1 interrupt, enable transceive
sbr r16, (1<<UDRIE1) | (1<<TXCIE1) | (1<<TXEN1) ; enable TX UDRE and TXC0 interrupt, enable transceive
outr UCSR1B, r16
ret
; @end
@@ -481,7 +502,7 @@ comOnUart1StartTx:
comOnUart1StopTx:
inr r16, UCSR1B
cbr r16, (1<<UDRIE1) | (1<<TXCIE1) | (1<<TXEN1) ; disable TX UDRE and TXC1 interrupt, enable transceive
cbr r16, (1<<UDRIE1) | (1<<TXCIE1) | (1<<TXEN1) ; disable TX UDRE and TXC0 interrupt, enable transceive
outr UCSR1B, r16
ret
; @end
@@ -499,7 +520,7 @@ comOnUart1StopTx:
comOnUart1SetAttnInput:
cbi COM_ATTN1_DDR, COM_ATTN1_PIN ; set ATTN as input
.ifdef COM_ATTN1_PUE
; cbi COM_ATTN1_PUE, COM_ATTN_PIN ; disable pullup on ATTN
; cbi COM_ATTN1_PUE, COM_ATTN_PIN ; disable pullup on ATTN
.else
cbi COM_ATTN1_OUTPUT, COM_ATTN1_PIN ; disable pullup on ATTN
.endif
@@ -636,7 +657,7 @@ ComOnUart1_TxCharIsr:
; @clobbers none
ComOnUart1AttnChangeIsr:
ComOnUart1_AttnChangeIsr:
push r15
in r15, SREG
rcall ComOnUart1_HandleAttnChange
@@ -680,19 +701,19 @@ ComOnUart1_HandleAttnChange:
; @clobbers R16 (R17, X)
comOnUart1ActOnAttn:
ldd r16, Y+UART_HW2_IFACE_OFFS_MODE
rcall comOnUart1IsAttnLow ; (none)
brcc comOnUart1ActOnAttn_attnHigh
; ATTN low
ldd r16, Y+UART_HW2_IFACE_OFFS_MODE
cpi r16, UART_HW2_MODE_IDLE
brne comOnUart1ActOnAttn_end ; not idle
rcall comOnUart1StartReading ; (R16, R17, X)
rjmp comOnUart1ActOnAttn_end
; ATTN high
comOnUart1ActOnAttn_attnHigh:
cpi r16, UART_HW2_MODE_SKIPPING
cpi r16, UART_HW2_MODE_SKIPPING
brne comOnUart1ActOnAttn_end
ldi r16, UART_HW2_MODE_IDLE
ldi r16, UART_HW2_MODE_IDLE ; leave skipping mode
rcall comOnUart1SetMode ; (R17)
comOnUart1ActOnAttn_end:
ret
@@ -723,7 +744,7 @@ comOnUart1RxCharIsr:
; store char
ldd xl, Y+UART_HW2_IFACE_OFFS_BUFPOS_LOW
ldd xh, Y+UART_HW2_IFACE_OFFS_BUFPOS_HIGH
st X+, r16
st X+, r16 ; last byte written
std Y+UART_HW2_IFACE_OFFS_BUFPOS_LOW, xl
std Y+UART_HW2_IFACE_OFFS_BUFPOS_HIGH, xh
; handle counters
@@ -792,7 +813,7 @@ comOnUart1TxUdreIsr:
std Y+UART_HW2_IFACE_OFFS_BUFPOS_HIGH, xh
; send byte
outr UDR1, r16 ; send byte
; decrease counter
; decreased counter
dec r17
std Y+UART_HW2_IFACE_OFFS_BUFLEFT, r17
brne comOnUart1TxUdreIsr_end ; still bytes left to send, jump
@@ -813,7 +834,7 @@ comOnUart1TxUdreIsr_end:
; ---------------------------------------------------------------------------
; @routine comOnUart1TxCharIsr @global
;
; Handler for TXC1 interrupt called when the last byte has been completely sent and
; Handler for TXC0 interrupt called when the last byte has been completely sent and
; the data register is empty.
;
; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_MODE)