From e840bfd9e685cc44e0347893d77e82a9975a8878 Mon Sep 17 00:00:00 2001
From: Martin Preuss <martin@aquamaniac.de>
Date: Sat, 25 Jan 2025 03:16:02 +0100
Subject: [PATCH] avr: t03 runs in basic mode now, flashing of AtTiny841
 finally works!!

---
 avr/devices/t03/0BUILD             |  19 ++
 avr/devices/t03/boot.asm           | 188 +-------------
 avr/devices/t03/debugboot.asm      | 398 +++++++++++++++++++++++++++++
 avr/devices/t03/main.asm           |  87 ++++---
 avr/modules/bootloader/main.asm    |  39 ++-
 avr/modules/flash/eeprom.asm       |  64 +++++
 avr/modules/flash/flash.asm        |  56 ----
 avr/modules/flash/flashprocess.asm |  37 ++-
 avr/modules/flash/io.asm           |   9 +-
 avr/modules/flash/io_uart1.asm     | 342 +++++++++++++++++++++++--
 avr/modules/flash/wait.asm         |  19 +-
 11 files changed, 916 insertions(+), 342 deletions(-)
 create mode 100644 avr/devices/t03/debugboot.asm
 create mode 100644 avr/modules/flash/eeprom.asm

diff --git a/avr/devices/t03/0BUILD b/avr/devices/t03/0BUILD
index 4dc1f0b..7351c28 100644
--- a/avr/devices/t03/0BUILD
+++ b/avr/devices/t03/0BUILD
@@ -39,6 +39,25 @@
   </target>
 
 
+
+  <target type="AvrHexFile" name="t03_debugboot" >
+
+    <includes type="avrasm" >
+      -I $(builddir)
+      -I $(srcdir)
+      -I $(topsrcdir)/avr
+      -I $(topbuilddir)/avr
+    </includes>
+
+
+    <sources type="avrasm" >
+      debugboot.asm
+    </sources>
+
+
+  </target>
+
+
   <subdirs>
   </subdirs>
 
diff --git a/avr/devices/t03/boot.asm b/avr/devices/t03/boot.asm
index 3f3d730..a2c6fb1 100644
--- a/avr/devices/t03/boot.asm
+++ b/avr/devices/t03/boot.asm
@@ -115,7 +115,6 @@ firmwareStart:   rjmp main ; will be overwritten when flashing
 
 
 main:
-;  rjmp debugEchoUart1
   rjmp bootLoader ; this routine is in modules/bootloader/main.asm
 
 
@@ -124,16 +123,16 @@ main:
 ; ***************************************************************************
 ; includes
 
-.include "modules/uart_hw/raw_uart1.asm"
+;.include "modules/uart_hw/raw_uart1.asm"
 .include "modules/com2/crc.asm"
-.include "common/crc8.asm"
 .include "common/utils_wait_fixed.asm"
 .include "common/utils_copy_from_flash.asm"
 .include "common/utils_copy_sdram.asm"
 .include "modules/flash/defs.asm"
+.include "modules/flash/eeprom.asm"
 .include "modules/flash/io.asm"
 .include "modules/flash/io_uart1.asm"
-.include "modules/flash/flash.asm"
+.include "modules/flash/flash4p.asm"
 .include "modules/flash/flashprocess.asm"
 .include "modules/flash/wait.asm"
 .include "modules/bootloader/main.asm"
@@ -158,184 +157,3 @@ systemSetSpeed:
 
 
 
-
-; debug
-
-debugEchoUart1:
-  cli
-  ; setup stack
-  .ifdef SPH               ; if SPH is defined
-    ldi r16, High(RAMEND)
-    out SPH, r16           ; init MSB stack pointer
-  .endif
-  ldi r16, Low(RAMEND)
-  out SPL, r16             ; init LSB stack pointer
-
-  rcall systemSetSpeed
-
-  sbi LED_DDR, LED_PINNUM  ; out
-  cbi LED_PORT, LED_PINNUM ; on
-
-  ; set baudrate
-.if clock == 8000000
-  ldi r16, 25 ; (19.2Kb/s at 8MHz)
-  ldi r17, 0
-.endif
-
-.if clock == 1000000
-  ldi r16, 3  ; (19.2Kb/s at 1MHz)
-  ldi r17, 0  
-.endif
-
-  sts UBRR1H, r17
-  sts UBRR1L, r16
-
-  ; set character format (asynchronous USART, 8-bit, one stop bit, no parity)
-  ldi r16, (3<<UCSZ10)
-  sts UCSR1C, r16
-
-  ; enable transceiver
-  lds r16, UCSR1B
-;  cbr r16, (1<<UDRIE1)  ; disable DRE interrupt
-  ori r16, (1<<RXEN1) | (1<<TXEN1)   ; enable transmit and receive
-  sts UCSR1B, r16
-
-
-  ldi zl, LOW(debugString*2)
-  ldi zh, HIGH(debugString*2)
-  rcall debugWriteString
-
-debugEchoUart1_loop:
-    rcall debugReadByte
-    sbi LED_PIN, LED_PINNUM                 ; toggle
-    rcall debugWriteByte
-  rjmp debugEchoUart1_loop
-
-
-
-debugReadByte:
-    lds r17, UCSR1A
-    sbrs r17, RXC1
-  rjmp debugReadByte
-  lds r16, UDR1
-  ret
-
-
-debugWriteByte:
-    lds r17, UCSR1A
-    sbrs r17, UDRE1
-  rjmp debugWriteByte
-;    sbr r17, (1<<TXC1)
-;    sts UCSR1A, r17
-  sts UDR1, r16
-  ret
-
-
-
-debugWriteString:
-    lpm r16, Z+
-    tst r16
-    breq debugWriteString_done
-    rcall debugWriteByte
-  rjmp debugWriteString
-debugWriteString_done:
-  ret
-
-
-debugString: .db "Hello", 13, 10, 0
-
-
-
-debugPrintLoop:
-  sbi LED_PORT, LED_PINNUM ; off
-  ; enable transceiver
-  lds r17, UCSR1B
-;  cbr r17, (1<<UDRIE1)  ; disable DRE interrupt
-  ori r17, (1<<RXEN1) | (1<<TXEN1)   ; enable transmit and receive
-  sts UCSR1B, r17
-
-debugPrintLoop1:
-  push r16
-    rcall debugPrintHexByte
-    ldi r16, 13
-    rcall debugPrintOneChar    ; (r17)
-    ldi r16, 10
-    rcall debugPrintOneChar    ; (r17)
-    ldi r16, 10
-    rcall flashWaitForMulti100ms
-  pop r16
-  rjmp debugPrintLoop1
-
-
-
-; ---------------------------------------------------------------------------
-; @routine debugPrintHexByte
-;
-; Convert a give byte into HEX and write it to USART1.
-;
-; @return CFLAG set if okay, cleared on error
-; @param  R16 byte to convert to print
-; @clobbers r16, r20 (r17)
-
-debugPrintHexByte:
-  mov r20, r16
-  swap r16
-  rcall debugNibbleToAscii ; write high nibble (r17)
-  rcall debugPrintOneChar  ; (r17)
-  brcc debugPrintHexByte_error
-  mov r16, r20
-  rcall debugNibbleToAscii ; write low nibble (r17)
-  rcall debugPrintOneChar  ; (r17)
-  brcc debugPrintHexByte_error
-  sec
-  ret
-debugPrintHexByte_error:
-  clc
-  ret
-; @end
-
-
-
-; ---------------------------------------------------------------------------
-; @routine debugNibbleToAscii
-;
-; Convert a nibble to an ASCII char.
-; @return R16 ASCII representation of that nibble (e.g. '0' for 0)
-; @param  R16 byte (in bits 0-3)
-; @clobbers r17
-
-debugNibbleToAscii:
-  andi r16, 0xf
-  cpi r16, 10
-  brcs debugNibbleToAscii_l1
-  ldi r17, 7
-  add r16, r17
-debugNibbleToAscii_l1:
-  ldi r17, '0'
-  add r16, r17
-  ret
-; @end
-
-
-
-; ---------------------------------------------------------------------------
-; @routine debugPrintOneChar
-;
-; Write one byte to UART1.
-; @param  R16 byte to send
-; @clobbers r17
-
-debugPrintOneChar:
-    lds r17, UCSR1A
-    sbrs r17, UDRE1
-  rjmp debugPrintOneChar
-  sbr r17, (1<<TXC1)
-  sts UCSR1A, r17
-  sts UDR1, r16
-  sec
-  ret
-; @end
-
-
-
-
diff --git a/avr/devices/t03/debugboot.asm b/avr/devices/t03/debugboot.asm
new file mode 100644
index 0000000..e901ea4
--- /dev/null
+++ b/avr/devices/t03/debugboot.asm
@@ -0,0 +1,398 @@
+; ***************************************************************************
+; Source file for base system node on AtTiny 84
+;
+; This is for the maintenance system (i.e. the flash loader).
+;
+; All definitions and changes should go into this file.
+; ***************************************************************************
+
+;.equ clock=1000000 ; Define the clock frequency
+.equ clock=8000000 ; Define the clock frequency
+
+.nolist
+.include "include/tn841def.inc" ; Define device ATtiny841
+.list
+
+.include "./defs.asm"
+.include "defs_all.asm"
+
+
+
+; ***************************************************************************
+; defines
+
+; ---------------------------------------------------------------------------
+; generic
+
+.include "common/utils_wait.asm"
+.include "modules/com2/defs.asm"
+.include "modules/comproto/defs.asm"
+
+
+
+; ---------------------------------------------------------------------------
+; firmware settings
+
+.equ FIRMWARE_VERSION_MAJOR       = 0
+.equ FIRMWARE_VERSION_MINOR       = 0
+.equ FIRMWARE_VERSION_PATCHLEVEL  = 1
+
+
+;#define COM_ACCEPT_ALL_DEST 1
+
+
+
+; ---------------------------------------------------------------------------
+; LED
+
+.equ LED_DDR             = DDRB
+.equ LED_PORT            = PORTB
+.equ LED_PIN             = PINB
+.equ LED_PINNUM          = PORTB2
+
+
+; ***************************************************************************
+; code segment
+
+.cseg
+.org 0x0000
+
+
+
+; ---------------------------------------------------------------------------
+; Reset and interrupt vectors
+
+        rjmp main                 ;  1: RESET             Reset vector  use this for flashed system
+	reti                      ;  2: INT0              External Interrupt Request 0
+	reti                      ;  3: PCINT0            Pin Change Interrupt 0
+	reti                      ;  4: PCINT1            Pin Change Interrupt 1
+	reti                      ;  5: WDT               Watchdog Time-out
+	reti                      ;  6: TIM1_CAPT         Timer/Counter1 Capture Event
+	reti                      ;  7: TIM1_COMPA (OC1A) Timer/Counter1 Compare Match A
+	reti                      ;  8: TIM1_COMPB (OC1B) Timer/Counter1 Compare Match B
+	reti                      ;  9: TIM1_OVF (OVF1)   Timer/Counter1 Overflow
+        reti                      ; 10: TIM0_COMPA (OC0A) Timer/Counter0 Compare Match A
+	reti                      ; 11: TIM0_COMPB (OC0B) Timer/Counter0 Compare Match B
+	reti                      ; 12: TIM0_OVF (OVF0)   Timer/Counter0 Overflow
+	reti                      ; 13: ANA_COMP0         Analog Comparator 0
+        reti                      ; 14: ADC_READY         ADC Conversion Complete
+        reti                      ; 15: EE_RDY (ERDY)     EEPROM Ready
+        reti                      ; 16: ANA_COMP1         Analog Comparator 1
+        reti                      ; 17: TIM2_CAPT         Timer/Counter2 Capture Event
+        reti                      ; 18: TIM2_COMPA (OC2A) Timer/Counter2 Compare Match A
+        reti                      ; 19: TIM2_COMPB (OC2B) Timer/Counter2 Compare Match B
+        reti                      ; 20: TIM2_OVF (OVF2)   Timer/Counter2 Overflow
+        reti                      ; 21: SPI               SPI Serial Transfer Complete
+        reti                      ; 22: USART0_RXS        USART0 Rx Start
+        reti                      ; 23: USART0_RXC        USART0 Rx Complete
+        reti                      ; 24: USART0_DRE        USART0 Data Register Empty
+        reti                      ; 25: USART0_TXC        USART0 Tx Complete
+        reti                      ; 26: USART1_RXS        USART1 Rx Start
+        reti                      ; 27: USART1_RXC        USART1 Rx Complete
+        reti                      ; 28: USART1_DRE        USART1 Data Register Empty
+        reti                      ; 29: USART1_TXC        USART1 Tx Complete
+        reti                      ; 30: TWI               Two-Wire-Interface
+        reti                      ; 31: RESERVED          reserved
+
+
+
+devInfoBlock:        ; 12 bytes
+devInfoManufacturer: .db 'A', 'Q', 'U', 'A'
+devInfoId:           .db DEVICEINFO_ID, 0
+devInfoVersion:      .db DEVICEINFO_VERSION, DEVICEINFO_REVISION             ; version, revision
+firmwareVersion:     .db FIRMWARE_VARIANT_BOOT, FIRMWARE_VERSION_MAJOR
+                     .db FIRMWARE_VERSION_MINOR, FIRMWARE_VERSION_PATCHLEVEL
+
+firmwareStart:   rjmp main ; will be overwritten when flashing
+
+
+
+; ***************************************************************************
+; main code
+
+
+.org BOOTLOADER_ADDR
+
+
+main:
+  rjmp debugFlash
+;  rjmp debugEchoUart1
+;  rjmp bootLoader ; this routine is in modules/bootloader/main.asm
+
+
+
+
+; ***************************************************************************
+; includes
+
+;.include "modules/uart_hw/raw_uart1.asm"
+.include "modules/com2/crc.asm"
+.include "common/utils_wait_fixed.asm"
+.include "common/utils_copy_from_flash.asm"
+.include "common/utils_copy_sdram.asm"
+.include "modules/flash/defs.asm"
+;.include "modules/flash/eeprom.asm"
+;.include "modules/flash/io.asm"
+;.include "modules/flash/io_uart1.asm"
+.include "modules/flash/flash4p.asm"
+;.include "modules/flash/flashprocess.asm"
+.include "modules/flash/wait.asm"
+;.include "modules/bootloader/main.asm"
+
+
+
+systemSetSpeed:
+.if clock == 1000000
+  ldi r17, 0xd8
+  ldi r16, (1<<CLKPS1) | (1<<CLKPS0) ; SUT=0, CLKPS=0011b
+  sts CCP, r17
+  sts CLKPR, r16
+.endif
+
+.if clock == 8000000
+  ldi r17, 0xd8
+  clr r16           ; SUT=0, CLKPS=0
+  sts CCP, r17
+  sts CLKPR, r16
+.endif
+  ret
+
+
+
+
+
+.dseg
+
+debugFlashBuffer: .byte 32
+flashUid:         .byte 4
+
+
+.cseg
+
+
+
+debugFlash:
+  cli
+  ; setup stack
+  .ifdef SPH               ; if SPH is defined
+    ldi r16, High(RAMEND)
+    out SPH, r16           ; init MSB stack pointer
+  .endif
+  ldi r16, Low(RAMEND)
+  out SPL, r16             ; init LSB stack pointer
+
+  rcall systemSetSpeed
+
+  sbi LED_DDR, LED_PINNUM  ; out
+  cbi LED_PORT, LED_PINNUM ; on
+
+  ; set baudrate
+.if clock == 8000000
+  ldi r16, 25 ; (19.2Kb/s at 8MHz)
+  ldi r17, 0
+.endif
+
+.if clock == 1000000
+  ldi r16, 3  ; (19.2Kb/s at 1MHz)
+  ldi r17, 0  
+.endif
+
+  sts UBRR1H, r17
+  sts UBRR1L, r16
+
+  ; set character format (asynchronous USART, 8-bit, one stop bit, no parity)
+  ldi r16, (3<<UCSZ10)
+  sts UCSR1C, r16
+
+  ; enable transceiver
+  lds r16, UCSR1B
+;  cbr r16, (1<<UDRIE1)  ; disable DRE interrupt
+  ori r16, (1<<RXEN1) | (1<<TXEN1)   ; enable transmit and receive
+  sts UCSR1B, r16
+
+
+  ldi xl, LOW(debugFlashBuffer)
+  ldi xh, HIGH(debugFlashBuffer)
+  ldi r17, 32
+  clr r16
+debugFlash_loop1:
+    st X+, r16
+    inc r16
+    dec r17
+  brne debugFlash_loop1
+
+  rcall Flash_Init
+  ldi yl, LOW(debugFlashBuffer)
+  ldi yh, HIGH(debugFlashBuffer)
+  ldi zl, LOW(0x500)
+  ldi zh, HIGH(0x500)
+  ldi r17, 32
+  rcall Flash_WriteData
+  
+  rcall Flash_Fini
+
+debugFlash_loop2:
+    sbi LED_PIN, LED_PINNUM                 ; toggle
+    ldi zl, LOW(0x500)
+    ldi zh, HIGH(0x500)
+    ldi r18, 64
+    rcall debugDumpFlash
+  
+    ldi r16, 50
+    rcall flashWaitForMulti100ms   ; print every 5 secs
+  rjmp debugFlash_loop2
+  ret
+
+
+
+debugWriteString:
+    lpm r16, Z+
+    tst r16
+    breq debugWriteString_done
+    rcall debugPrintOneChar    ; (r17)
+  rjmp debugWriteString
+debugWriteString_done:
+  ret
+
+
+debugString: .db "FLASH", 13, 10, 0
+
+
+#if 0
+debugPrintLoop:
+  sbi LED_PORT, LED_PINNUM ; off
+  ; enable transceiver
+  lds r17, UCSR1B
+;  cbr r17, (1<<UDRIE1)  ; disable DRE interrupt
+  ori r17, (1<<RXEN1) | (1<<TXEN1)   ; enable transmit and receive
+  sts UCSR1B, r17
+
+debugPrintLoop1:
+  push r16
+    rcall debugPrintHexByte
+    ldi r16, 13
+    rcall debugPrintOneChar    ; (r17)
+    ldi r16, 10
+    rcall debugPrintOneChar    ; (r17)
+    ldi r16, 10
+    rcall flashWaitForMulti100ms
+  pop r16
+  rjmp debugPrintLoop1
+#endif
+
+
+; @param Z start of FLASH to dump
+; @param r18: number of bytes to dump
+
+debugDumpFlash:
+  push zh
+    push zl
+      ldi zl, LOW(debugString*2)
+      ldi zh, HIGH(debugString*2)
+      rcall debugWriteString
+    pop zl
+  pop zh
+debugDumpFlash_loop1:
+  mov r16, zh
+  rcall debugPrintHexByte
+  mov r16, zl
+  rcall debugPrintHexByte
+  ldi r16, ':'
+  rcall debugPrintOneChar    ; (r17)
+  ldi r16, ' '
+  rcall debugPrintOneChar    ; (r17)
+  ldi r19, 16
+debugDumpFlash_loop2:
+      lpm r16, Z+
+      rcall debugPrintHexByte
+      ldi r16, ' '
+      rcall debugPrintOneChar    ; (r17)
+      dec r18
+      breq debugDumpFlash_done
+      dec r19
+    brne debugDumpFlash_loop2
+    ldi r16, 13
+    rcall debugPrintOneChar    ; (r17)
+    ldi r16, 10
+    rcall debugPrintOneChar    ; (r17)
+  rjmp debugDumpFlash_loop1
+debugDumpFlash_done:
+  ldi r16, 13
+  rcall debugPrintOneChar    ; (r17)
+  ldi r16, 10
+  rcall debugPrintOneChar    ; (r17)
+  ret
+
+
+
+; ---------------------------------------------------------------------------
+; @routine debugPrintHexByte
+;
+; Convert a give byte into HEX and write it to USART1.
+;
+; @return CFLAG set if okay, cleared on error
+; @param  R16 byte to convert to print
+; @clobbers r16, r20 (r17)
+
+debugPrintHexByte:
+  mov r20, r16
+  swap r16
+  rcall debugNibbleToAscii ; write high nibble (r17)
+  rcall debugPrintOneChar  ; (r17)
+  brcc debugPrintHexByte_error
+  mov r16, r20
+  rcall debugNibbleToAscii ; write low nibble (r17)
+  rcall debugPrintOneChar  ; (r17)
+  brcc debugPrintHexByte_error
+  sec
+  ret
+debugPrintHexByte_error:
+  clc
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine debugNibbleToAscii
+;
+; Convert a nibble to an ASCII char.
+; @return R16 ASCII representation of that nibble (e.g. '0' for 0)
+; @param  R16 byte (in bits 0-3)
+; @clobbers r17
+
+debugNibbleToAscii:
+  andi r16, 0xf
+  cpi r16, 10
+  brcs debugNibbleToAscii_l1
+  ldi r17, 7
+  add r16, r17
+debugNibbleToAscii_l1:
+  ldi r17, '0'
+  add r16, r17
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine debugPrintOneChar
+;
+; Write one byte to UART1.
+; @param  R16 byte to send
+; @clobbers r17
+
+debugPrintOneChar:
+    lds r17, UCSR1A
+    sbrs r17, UDRE1
+  rjmp debugPrintOneChar
+  sbr r17, (1<<TXC1)
+  sts UCSR1A, r17
+  sts UDR1, r16
+  sec
+  ret
+; @end
+
+
+
+
diff --git a/avr/devices/t03/main.asm b/avr/devices/t03/main.asm
index 7f51bd5..c9c8376 100644
--- a/avr/devices/t03/main.asm
+++ b/avr/devices/t03/main.asm
@@ -115,6 +115,7 @@
         reti                      ; 31: RESERVED          reserved
 
 
+
 devInfoBlock:        ; 12 bytes
 devInfoManufacturer: .db 'A', 'Q', 'U', 'A'
 devInfoId:           .db DEVICEINFO_ID, 0
@@ -122,38 +123,8 @@ devInfoVersion:      .db DEVICEINFO_VERSION, DEVICEINFO_REVISION             ; v
 firmwareVersion:     .db FIRMWARE_VARIANT_TEMP_WINDOW, FIRMWARE_VERSION_MAJOR
                      .db FIRMWARE_VERSION_MINOR, FIRMWARE_VERSION_PATCHLEVEL
 
-firmwareStart:   rjmp main
-
-
-; ***************************************************************************
-; includes
-
-.include "common/utils.asm"
-.include "common/utils_wait_fixed.asm"
-.include "common/utils_copy_from_flash.asm"
-.include "common/utils_copy_sdram.asm"
-.include "common/crc8.asm"
-
-.include "modules/basetimer/main.asm"
-.include "modules/led_simple/main.asm"
-
-
-
-; ***************************************************************************
-; data in SRAM
-
-.dseg
-
-programRamBegin:
-; nothing for now
-programRamEnd:
-
-
-
-.cseg
-
-
-main:
+;firmwareStart:   rjmp main
+firmwareStart:
   cli
   ; setup stack
   .ifdef SPH               ; if SPH is defined
@@ -163,35 +134,41 @@ main:
   ldi r16, Low(RAMEND)
   out SPL, r16             ; init LSB stack pointer
 
+#if 0
   ; start by setting all ports as inputs and enable internal pull-up resistors
   ldi r16, 0xff
   clr r17
 .ifdef PORTA
   out DDRA, r17  ; all input
-  out PORTA, r16 ; enable pull-up on all
+  sts PUEA, r16 ; enable pull-up on all
 .endif
 
 .ifdef PORTB
   out DDRB, r17  ; all input
-  out PORTB, r16 ; enable pull-up on all
+  sts PUEB, r16 ; enable pull-up on all
 .endif
 
 .ifdef PORTC
   out DDRC, r17  ; all input
-  out PORTC, r16 ; enable pull-up on all
+  sts PUEC, r16 ; enable pull-up on all
 .endif
 
+#endif
+
   rcall systemSetSpeed
 ;  rcall watchdogOff        ; turn off watchdog timer (sometimes it stays on after reboot)
 
+  rcall Utils_Init
+  rcall BaseTimer_Init
+  rcall LedSimple_Init
+
   rcall Utils_SetupUid
 
-  rcall LedSimple_Init
+  sbi LED_SIMPLE_DDR, LED_SIMPLE_PINNUM  ; out
+  sbi LED_SIMPLE_PORT, LED_SIMPLE_PINNUM ; off
 
   sei
 main_loop:
-    ; do something
-    
     ; only modify SE, SM1 and SM0
     cli
     in r16, MCUCR
@@ -202,6 +179,9 @@ main_loop:
     out MCUCR, r16
     sei ; make sure interrupts really are enabled
     sleep                      ; sleep, wait for interrupt
+
+  rcall BaseTimer_Run
+
   rjmp main_loop
 
 
@@ -237,3 +217,34 @@ onSystemTimerTick:
 
 
 
+
+
+; ***************************************************************************
+; includes
+
+.include "common/utils.asm"
+.include "common/utils_wait_fixed.asm"
+.include "common/utils_copy_from_flash.asm"
+.include "common/utils_copy_sdram.asm"
+.include "common/crc8.asm"
+.include "modules/flash/wait.asm"
+.include "modules/basetimer/main.asm"
+.include "modules/led_simple/main.asm"
+
+
+
+; ***************************************************************************
+; data in SRAM
+
+.dseg
+
+programRamBegin:
+; nothing for now
+flashUid:         .byte 4
+programRamEnd:
+
+
+
+
+
+
diff --git a/avr/modules/bootloader/main.asm b/avr/modules/bootloader/main.asm
index 6684692..e295abf 100644
--- a/avr/modules/bootloader/main.asm
+++ b/avr/modules/bootloader/main.asm
@@ -53,25 +53,50 @@ bootLoader:
 ;  rcall watchdogOff        ; turn off watchdog timer (sometimes it stays on after reboot)
 
   sbi LED_DDR, LED_PINNUM  ; out
-  cbi LED_PORT, LED_PINNUM ; on
-  ldi r16, 30
-  rcall flashWaitForMulti100ms
+  sbi LED_PORT, LED_PINNUM ; off
+
+  ldi r19, 20 ; loop count
+  ldi r20, 2  ; on time
+  ldi r21, 2  ; off time
+  rcall bootLoaderBlinkLed
+
   rcall checkFlash                          ; (r16, r17, r18, r19, r20, r22, x, y, z)
   brcc bootLoader_startFirmware             ; no flash process, try to start installed firmware
   rcall flashProcess                        ; received a FLASH START msg, handle flashing
   brcc bootLoader_waitAndRestartBootLoader
   ; try to start firmware
 bootLoader_startFirmware:
-  cbi LED_PORT, LED_PINNUM         ; on
+  ldi r19, 20 ; loop count
+  ldi r20, 4  ; on time
+  ldi r21, 1  ; off time
+  rcall bootLoaderBlinkLed
   rjmp firmwareStart
 bootLoader_waitAndRestartBootLoader:
-  sbi LED_PORT, LED_PINNUM         ; off
-  ldi r16, 20
-  rcall flashWaitForMulti100ms
+  ldi r19, 15 ; loop count
+  ldi r20, 1  ; on time
+  ldi r21, 8  ; off time
+  rcall bootLoaderBlinkLed
   rjmp bootLoader
 
 
 
+; @param r19 loop count
+; @param r20 on time
+; @param r21 off time
+; @clobbers (R16, R18, R22, R24, R25)
+
+bootLoaderBlinkLed:
+    cbi LED_PORT, LED_PINNUM ; on
+    mov r16, r20
+    rcall flashWaitForMulti100ms  ; (R16, R18, R22, R24, R25)
+    sbi LED_PORT, LED_PINNUM ; on
+    mov r16, r21
+    rcall flashWaitForMulti100ms  ; (R16, R18, R22, R24, R25)
+    dec r19
+  brne bootLoaderBlinkLed  
+  ret
+
+
 bootClcRet:
   clc
 bootRet:
diff --git a/avr/modules/flash/eeprom.asm b/avr/modules/flash/eeprom.asm
new file mode 100644
index 0000000..5c6f909
--- /dev/null
+++ b/avr/modules/flash/eeprom.asm
@@ -0,0 +1,64 @@
+; ***************************************************************************
+; copyright   : (C) 2025 by Martin Preuss
+; email       : martin@libchipcard.de
+;
+; ***************************************************************************
+; * This file is part of the project "AqHome".                              *
+; * Please see toplevel file COPYING of that project for license details.   *
+; ***************************************************************************
+
+
+; ---------------------------------------------------------------------------
+; flashReadEepromIncr
+;
+; Read a byte from EEPROM (see example in ATtiny24/44/84 manual p.19).
+;
+; IN:
+; - X: EEPROM Address to read from
+; OUT:
+; - R16: byte read
+; - X: EEPROM Address incremented
+; REGS: R16
+
+flashReadEepromIncr:
+  sbic EECR, EEPE          ; wait for previous write to complete (if any)
+    rjmp flashReadEepromIncr
+  out EEARH, xh            ; set EEPROM address
+  out EEARL, xl
+  sbi EECR, EERE           ; start EEPROM read by writing EERE
+  in r16, EEDR             ; read data from data register
+  adiw xh:xl, 1
+  ret
+
+
+
+; ---------------------------------------------------------------------------
+; @routine flashReadUidIntoSdram
+;
+; Read UID from EEPROM.
+;
+; @clobbers R16, X, Y
+
+flashReadUidIntoSdram:
+  ldi yh, HIGH(flashUid)
+  ldi yl, LOW(flashUid)
+  push r15
+    in r15, SREG
+    cli
+    ldi xl, LOW(EEPROM_OFFS_UUID)
+    ldi xh, HIGH(EEPROM_OFFS_UUID)
+    rcall flashReadEepromIncr ; (R16)
+    st Y+, r16
+    rcall flashReadEepromIncr ; (R16)
+    st Y+, r16
+    rcall flashReadEepromIncr ; (R16)
+    st Y+, r16
+    rcall flashReadEepromIncr ; (R16)
+    st Y+, r16
+    out SREG, r15
+  pop r15
+  ret
+; @end
+
+
+
diff --git a/avr/modules/flash/flash.asm b/avr/modules/flash/flash.asm
index 0210efe..60fa2ca 100644
--- a/avr/modules/flash/flash.asm
+++ b/avr/modules/flash/flash.asm
@@ -173,62 +173,6 @@ flashDoSpm_wait:                ; wait for possibly previous SPM to complete
 
 
 
-; ---------------------------------------------------------------------------
-; flashReadEepromIncr
-;
-; Read a byte from EEPROM (see example in ATtiny24/44/84 manual p.19).
-;
-; IN:
-; - X: EEPROM Address to read from
-; OUT:
-; - R16: byte read
-; - X: EEPROM Address incremented
-; REGS: R16
-
-flashReadEepromIncr:
-  sbic EECR, EEPE          ; wait for previous write to complete (if any)
-    rjmp flashReadEepromIncr
-  out EEARH, xh            ; set EEPROM address
-  out EEARL, xl
-  sbi EECR, EERE           ; start EEPROM read by writing EERE
-  in r16, EEDR             ; read data from data register
-  adiw xh:xl, 1
-  ret
-
-
-
-; ---------------------------------------------------------------------------
-; @routine flashReadUidIntoSdram
-;
-; Read UID from EEPROM.
-;
-; @clobbers R16, X, Y
-
-flashReadUidIntoSdram:
-  ldi yh, HIGH(flashUid)
-  ldi yl, LOW(flashUid)
-  push r15
-    in r15, SREG
-    cli
-    ldi xl, LOW(EEPROM_OFFS_UUID)
-    ldi xh, HIGH(EEPROM_OFFS_UUID)
-    rcall flashReadEepromIncr ; (R16)
-    st Y+, r16
-    rcall flashReadEepromIncr ; (R16)
-    st Y+, r16
-    rcall flashReadEepromIncr ; (R16)
-    st Y+, r16
-    rcall flashReadEepromIncr ; (R16)
-    st Y+, r16
-    out SREG, r15
-  pop r15
-  ret
-; @end
-
-
-
-
-
 FLASH_END:
 .equ MODULE_SIZE_FLASH = FLASH_END-FLASH_BEGIN
 
diff --git a/avr/modules/flash/flashprocess.asm b/avr/modules/flash/flashprocess.asm
index f09191e..d7f215c 100644
--- a/avr/modules/flash/flashprocess.asm
+++ b/avr/modules/flash/flashprocess.asm
@@ -48,7 +48,6 @@ checkFlash:
   rcall ioRawSendMsg                   ; (r16, r17, X)
 
   ldi r16, CPRO_CMD_FLASH_START
-  ldi r20, 10                          ; wait for up to 10s
   rcall ioWaitForGivenMsg              ; (r16, r17, r18, r19, r20, r22, X)
   brcc checkFlash_end
   
@@ -81,6 +80,7 @@ checkFlash_end:
 ; @clobbers r16, r20
 
 flashProcess:
+  rcall Flash_Init
 flashProcess_loop1:
     ; wait up to 10s for incoming FLASH_DATA message
     ldi r16, CPRO_CMD_FLASH_DATA
@@ -94,7 +94,8 @@ flashProcess_loop1:
     rcall flashProcessHandleFlashData  ; (R0, R1, R15, R16, R17, R18, R19, R20, Z)
   rjmp flashProcess_loop1
 flashProcess_endReceived:
-  rjmp flashProcessHandleFlashEnd
+  rcall flashProcessHandleFlashEnd
+  sec
 flashProcess_end:
   ret
 ; @end
@@ -163,27 +164,18 @@ flashProcessCheckFlashStart_notMe:
 ; @clobbers R0, R1, R18, Z (R15, R16, R17, R19, R20)
 
 flashProcessHandleFlashData:
-  adiw xh:xl, FLASH_MSG_OFFS_MSGLEN
-  ld r18, X                                  ; length (subtract 6)
-  cpi r18, 6                                 ; cmd(1), src(1), addr(4)
+  mov yl, xl
+  mov yh, xh
+  adiw yh:yl, FLASH_MSG_OFFS_MSGLEN
+  ld r17, Y                                  ; length (subtract 6)
+  cpi r17, 6                                 ; cmd(1), src(1), addr(4)
   brcs flashProcessHandleFlashData_badData
-  subi r18, 6                                ; remaining length
-  adiw xh:xl, FLASH_PACKET_DATA_OFFS_ADDR-FLASH_MSG_OFFS_MSGLEN
-  ld zl, X+                                  ; address (low)
-  ld zh, X+                                  ; address (high)
-  adiw xh:xl, 2                              ; ignore high bytes, points to first data byte now
-
-;  push zl
-;    push zh
-;flashProcessHandleFlashData_loop:
-;        ld r0, X+
-;        ld r1, X+
-;        rcall Flash_WriteIntoPage            ; (R15, R16, Z+)
-;        subi r18, 2
-;      brne flashProcessHandleFlashData_loop
-;    pop zh
-;  pop zl
-;  rcall Flash_FinishPage                     ; (R15, R16, R20)
+  subi r17, 6                                ; remaining length
+  adiw yh:yl, FLASH_PACKET_DATA_OFFS_ADDR-FLASH_MSG_OFFS_MSGLEN
+  ld zl, Y+                                  ; address (low)
+  ld zh, Y+                                  ; address (high)
+  adiw yh:yl, 2                              ; ignore high bytes, points to first data byte now
+  rcall Flash_WriteData                      ; (R0, R1, R16, R18, R19, R20, R24, R25, X)
   clr r16
   rjmp flashProcessHandleFlashData_sendResponse
 flashProcessHandleFlashData_badData:
@@ -206,6 +198,7 @@ flashProcessHandleFlashData_sendResponse:
 ; @clobbers r16, X (R17, R18, R19, R20)
 
 flashProcessHandleFlashEnd:
+  rcall Flash_Fini                       ; flash pending data
   rcall flashWaitFor100ms
   clr r16
   rcall flashProcessSendFlashResponse    ; (R16, R17, R18, R19, R20, X)
diff --git a/avr/modules/flash/io.asm b/avr/modules/flash/io.asm
index ee1073d..5e48948 100644
--- a/avr/modules/flash/io.asm
+++ b/avr/modules/flash/io.asm
@@ -25,25 +25,26 @@
 ; @clobbers: r16, r17, r20, X (r18, r19, r22)
 
 ioWaitForGivenMsg:
-    ldi r20, 100                     ; number of tries
+    ldi r20, 10                      ; number of tries
 ioWaitForGivenMsg_loop:
     push r16
       rcall ioRawWaitForValidMsg     ; (r16, r17, r18, r19, r22, X)
-    pop r16
+    pop r17                          ; pop into r17 (from r16)
     brcc ioWaitForGivenMsg_end
     ldi xl, LOW(flashRecvBuffer)
     ldi xh, HIGH(flashRecvBuffer)
     adiw xh:xl, COM2_MSG_OFFS_CMD
-    ld r17, X
+    ld r16, X
     sbiw xh:xl, COM2_MSG_OFFS_CMD
     cp r16, r17
     breq ioWaitForGivenMsg_gotIt
     cpi r16, CPRO_CMD_FLASH_END
     breq ioWaitForGivenMsg_gotIt
+    mov r16, r17                     ; put expected msg code back into r16 for next loop
     dec r20
   brne ioWaitForGivenMsg_loop
   clc
-  rjmp ioWaitForGivenMsg_end
+  ret
 ioWaitForGivenMsg_gotIt:
   sec
 ioWaitForGivenMsg_end:
diff --git a/avr/modules/flash/io_uart1.asm b/avr/modules/flash/io_uart1.asm
index c427286..60e1d3c 100644
--- a/avr/modules/flash/io_uart1.asm
+++ b/avr/modules/flash/io_uart1.asm
@@ -23,7 +23,30 @@
 ; @clobbers r16, r17
 
 ioRawInit:
-  rjmp UART_HW_Uart1_RawInit ; (R16, R17)
+  ; set baudrate
+.if clock == 8000000
+  ldi r16, 25 ; (19.2Kb/s at 8MHz)
+  ldi r17, 0
+.endif
+
+.if clock == 1000000
+  ldi r16, 3  ; (19.2Kb/s at 1MHz)
+  ldi r17, 0  
+.endif
+
+  sts UBRR1H, r17
+  sts UBRR1L, r16
+
+  ; set character format (asynchronous USART, 8-bit, one stop bit, no parity)
+  ldi r16, (3<<UCSZ10)
+  sts UCSR1C, r16
+
+  ; enable transceiver
+  lds r16, UCSR1B
+;  cbr r16, (1<<UDRIE1)  ; disable DRE interrupt
+  ori r16, (1<<RXEN1) | (1<<TXEN1)   ; enable transmit and receive
+  sts UCSR1B, r16
+  ret
 ;@end
 
 
@@ -37,11 +60,44 @@ ioRawInit:
 ioRawSendMsg:
   ldi xl, LOW(flashSendBuffer)
   ldi xh, HIGH(flashSendBuffer)
-  rjmp UART_HW_Uart1_RawSendPacket ; (r16, r17, X)
+  rjmp ioRawSendPacket          ; (r16, r17, X)
 ; @end
 
 
 
+; ---------------------------------------------------------------------------
+; @routine UART_HW_Uart1_RawSendPacket
+; Send packet.
+;
+; @param X buffer to send
+; @return CFLAG: set if okay (packet sent), cleared on error
+; @clobbers r16, r17, X
+
+ioRawSendPacket:
+  adiw xh:xl, 1
+  ld r17, X
+  sbiw xh:xl, 1
+  ldi r16, 3                     ; add DEST, LEN, CRC bytes
+  add r17, r16
+ioRawSendPacket_loop:
+      lds r16, UCSR1A
+      sbrs r16, UDRE1
+    rjmp ioRawSendPacket_loop
+    sbr r16, (1<<TXC1)
+    sts UCSR1A, r16
+    ld r16, X+
+    sts UDR1, r16
+    dec r17
+  brne ioRawSendPacket_loop
+  sec
+  ret
+; @end
+
+
+
+
+
+
 ; ---------------------------------------------------------------------------
 ; @routine ioRawWaitForValidMsg
 ; Wait for valid incoming msg
@@ -50,27 +106,273 @@ ioRawSendMsg:
 ; @clobbers: r16, r17, r18 (r19, r22, X)
 
 ioRawWaitForValidMsg:
-  rcall UART_HW_Uart1_EnableRawRecv     ; (R16)
-ioRawWaitForValidMsg_loop:
-    ldi xl, LOW(flashRecvBuffer)
-    ldi xh, HIGH(flashRecvBuffer)
-    ldi r16, COM2_MAINTENANCE_ADDR
-    ldi r17, FLASH_RECVBUFFER_MAXLEN-3
-    ldi r18, 10                         ; 10s
-    rcall UART_HW_Uart1_RawRecvPacket   ; (r16, r17, r18, r19, r22, X)
-    brcc ioRawWaitForValidMsg_error
-    ldi xl, LOW(flashRecvBuffer)
-    ldi xh, HIGH(flashRecvBuffer)
-    rcall com2CheckMessageInBuffer      ; (R16, R17, R18, R19, R20, X)
-  brcc ioRawWaitForValidMsg_loop     ; invalid msg, try next
-  rcall UART_HW_Uart1_DisableRawRecv    ; (R16)
-  sec
-  ret
-ioRawWaitForValidMsg_error:
-  rcall UART_HW_Uart1_DisableRawRecv    ; (R16)
+  ldi xl, LOW(flashRecvBuffer)
+  ldi xh, HIGH(flashRecvBuffer)
+  ldi r18, FLASH_RECVBUFFER_MAXLEN-3  ; maximum accepted msglen byte
+  ldi r20, 10                         ; 10 secs
+  rjmp ioRecvMsg
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine ioRecvMsg
+;
+; Wait for next message, if received check validity.
+; On error skip the currently received message.
+;
+; @return CFLAG set if okay, cleared on error
+; @param  r18   max accepted msglen size (buffersize-3)
+; @param  R20   max number of secs to wait for incoming message
+; @param  X     buffer to receive to
+; @clobbers (r16, r17, r18, r19, r20, r22)
+
+ioRecvMsg:
+  rcall ioRawRecvMsg                      ; (r16, r17, r18, r19, r20, r22)
+  brcc ioRecvMsg_error
+  push xl
+    push xh
+      rcall com2CheckMessageInBuffer      ; (R16, R17, R18, R19, R20, X)
+    pop xh
+  pop xl
+  brcs ioRecvMsg_end
+ioRecvMsg_error:
+  rcall ioRecvSkipMessage                 ; skip remainder of the message
   clc
+ioRecvMsg_end:
   ret
 ; @end
 
 
 
+; ---------------------------------------------------------------------------
+; @routine ioRecvSkipMessage
+;
+; skip all receiption data until a data pause of about 10ms
+;
+; @clobbers r16
+
+ioRecvSkipMessage:
+ioRecvSkipMessage_loop:
+    rcall ioRecvFlush               ; (r16)
+    ; wait for a data pause of 10ms
+    rcall ioRawRecvByteWithin10ms   ; (r20, r22)
+  brcs ioRecvSkipMessage_loop
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine ioRecvFlush
+;
+; flush receiption buffer.
+;
+; @clobbers r16
+
+ioRecvFlush:
+    lds r16, UCSR1A ; read status
+    sbrs r16, RXC1
+    ret
+    lds r16, UDR1   ; read data byte
+  rjmp ioRecvFlush
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine ioRawRecvMsg
+;
+; @return   CFLAG set if okay, cleared on error
+; @param    r18   max accepted msglen size (buffersize-3)
+; @param    R20   max number of secs to wait for incoming message
+; @param    X     buffer to receive to
+; @clobbers r16, r17, r19 (r18, r20, r22)
+
+ioRawRecvMsg:
+  lds r19, UCSR1A
+  cbr r19, (1<<FE1) | (1<<DOR1) | (1<<UPE1)
+  sts UCSR1A, r19               ; clear errors
+  ; wait for begin of message
+  rcall ioRawWaitForDataSeconds ; (r20, r22)
+  brcc ioRawRecvMsg_end
+  clr r19                       ; bytecounter
+  ; read first two bytes
+  ldi r17, 2                    ; 2 bytes: address byte, msg len
+  add r19, r17
+  rcall ioRawRecvBytes          ; (r16, r17, r18, r22)
+  brcc ioRawRecvMsg_error
+  cp r16, r20                   ; check size
+  brcc ioRawRecvMsg_error
+  inc r16                       ; account for checksum byte
+  ; read remaining bytes including checksum byte
+  mov r17, r16
+  add r19, r17
+  rcall ioRawRecvBytes          ; (r16, r17, r18, r22)
+  brcc ioRawRecvMsg_error
+  sub xl, r19                   ; let X point back to begin of message
+  sbc xh, r19
+  add xh, r19
+  sec
+  ret
+ioRawRecvMsg_error:
+  clc
+ioRawRecvMsg_end:
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine ioRawRecvBytes
+;
+; @return CFLAG set if okay (data available), cleared on error
+; @return r16 last byte received
+; @param r17 number of bytes to read
+; @param x buffer to receive to
+; @clobbers r16, r17 (r20, r22)
+
+ioRawRecvBytes:
+    rcall ioRawRecvByteWithin10ms ; (r20, r22)
+    brcc ioRawRecvBytes_end
+    st X+, r16
+    dec r17
+  brne ioRawRecvBytes
+  sec
+ioRawRecvBytes_end:
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine ioRawRecvByteWithin10ms
+;
+; Wait up to 10ms for incoming byte and read it.
+;
+; @return CFLAG set if okay (data available), cleared on error
+; @return r16 byte received (if CFLAG set)
+; @clobbers: r20, r22
+
+ioRawRecvByteWithin10ms:
+  rcall ioRawWaitForData10ms                   ; (R20, R22)
+  brcc ioRawRecvByteWithin10ms_end
+  lds r16, UCSR1A                              ; check for errors
+  andi r16, (1<<FE1) | (1<<DOR1) | (1<<UPE1)
+  brne ioRawRecvByteWithin10ms_error
+  lds r16, UDR1                                ; read data byte
+  sec
+  ret
+ioRawRecvByteWithin10ms_error:
+  clc
+ioRawRecvByteWithin10ms_end:
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine ioRawWaitForDataSeconds
+;
+; Wait for incoming data for max 1s
+;
+; @return CFLAG set if okay (data available), cleared on error
+; @param r20 maximum number of seconds to wait
+; @clobbers: r20, r22
+
+ioRawWaitForDataSeconds:
+ioRawWaitForDataSeconds_loop:
+    push r20
+      rcall ioRawWaitForData1s              ; (r20, r22)
+    pop r20
+    brcs ioRawWaitForDataSeconds_gotit
+    sbi LED_PIN, LED_PINNUM                 ; toggle
+    dec r20
+  brne ioRawWaitForDataSeconds_loop
+  clc
+ioRawWaitForDataSeconds_gotit:
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine ioRawWaitForData1s
+;
+; Wait for incoming data for max 1s
+;
+; @return CFLAG set if okay (data available), cleared on error
+; @clobbers: r20, r22
+
+ioRawWaitForData1s:
+  ldi r20, 100
+ioRawWaitForData1s_loop:
+    push r20
+      rcall ioRawWaitForData10ms   ; (R20, R22)
+    pop r20
+    brcs ioRawWaitForData1s_gotit
+    dec r20
+  brne ioRawWaitForData1s_loop
+  clc
+ioRawWaitForData1s_gotit:
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine ioRawWaitForData10ms
+;
+; Wait for incoming data for max 10 milliseconds.
+;
+; @return CFLAG set if okay (data available), cleared on error
+; @clobbers: r20, r22
+
+ioRawWaitForData10ms:
+.if clock == 8000000
+  ldi r20, 80
+.endif
+.if clock == 1000000
+  ldi r20, 10
+.endif
+ioRawWaitForData10ms_loop:
+    push r20
+      rcall ioRawWaitForData1000Cycles  ; (r20, r22)
+    pop r20
+    brcs ioRawWaitForData10ms_gotit
+    dec r20
+  brne ioRawWaitForData10ms_loop
+  clc
+ioRawWaitForData10ms_gotit:
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine ioRawWaitForData1000Cycles
+;
+; Wait for incoming data for max 1000 clock cycles
+; (about 1ms at 1MHz, 0.125 at 8MHz)
+;
+; @return CFLAG set if okay (packet received), cleared on error
+; @clobbers: r20, r22
+
+ioRawWaitForData1000Cycles:
+  ldi r20, 140                         ; 1
+ioRawWaitForData_loop:
+    lds r22, UCSR1A                    ; 2
+    sbrc r22, RXC1                     ; 2/3
+      rjmp ioRawWaitForData_gotit      ; 2
+    dec r20                            ; 1
+  brne ioRawWaitForData_loop           ; 1/2  -> 7 per loop, max about 1000
+  clc                                  ; 1
+  ret                                  ; 4
+ioRawWaitForData_gotit:
+  sec                                  ; 1
+  ret                                  ; 4
+; @end
+
+
+
+
diff --git a/avr/modules/flash/wait.asm b/avr/modules/flash/wait.asm
index d73d5ba..d62668c 100644
--- a/avr/modules/flash/wait.asm
+++ b/avr/modules/flash/wait.asm
@@ -27,7 +27,7 @@
 ; - nothing
 ; OUT:
 ; - nothing
-; REGS: R16 (R18, R22, R24, R25)
+; REGS: R16 (R22, R24)
 
 flashWaitDependingOnUid:
   lds r16, flashUid
@@ -46,20 +46,17 @@ flashWaitDependingOnUid_l1:
 ; - R16: number of 100ms loops
 ; OUT:
 ; - nothing
-; REGS: R16 (R18, R22, R24, R25)
+; REGS: R16 (R22, R24)
 
 flashWaitForMulti100ms:
 flashWaitForMulti100ms_loop:
-    rcall flashWaitFor100ms      ; (R18, R22, R24, R25)
+    rcall flashWaitFor100ms      ; (R22, R24)
     dec r16
   brne flashWaitForMulti100ms_loop
   ret
 
 
 
-
-
-
 ; ---------------------------------------------------------------------------
 ; wait for 100 milliseconds.
 ;
@@ -67,13 +64,15 @@ flashWaitForMulti100ms_loop:
 ; - nothing
 ; OUT:
 ; - nothing
-; REGS: R18 (R22, R24, R25)
+; REGS: R24 (R22)
 
 flashWaitFor100ms:
-  ldi r18, 100
+  ldi r24, 100
 flashWaitFor100ms_loop:
-    rcall flashWaitFor1ms      ; (R22, R24, R25)
-    dec r18
+    push r24
+      rcall flashWaitFor1ms      ; (R22, R24)
+    pop r24
+    dec r24
   brne flashWaitFor100ms_loop
   ret