try new implementation of UART code for m8515.
This commit is contained in:
Martin Preuss
102
avr/modules/uart_hw/attn.asm
Normal file
102
avr/modules/uart_hw/attn.asm
Normal file
@@ -0,0 +1,102 @@
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; ***************************************************************************
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; copyright : (C) 2025 by Martin Preuss
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; email : martin@libchipcard.de
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;
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; ***************************************************************************
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; * This file is part of the project "AqHome". *
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; * Please see toplevel file COPYING of that project for license details. *
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; ***************************************************************************
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; ***************************************************************************
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; code
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.cseg
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; ---------------------------------------------------------------------------
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; @routine ATTN_Init @global
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;
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; @clobbers R16
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ATTN_Init:
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.ifdef INT0
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.if COM_IRQ_BIT_ATTN == INT0
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M_IO_READ r16, MCUCR
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cbr r16, (1<<ISC01) | (1<<ISC00)
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sbr r16, (1<<ISC01) | (0<<ISC00) ; falling edge of ATTN
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; sbr r16, (0<<ISC01) | (0<<ISC00) ; low level triggers
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rcall ATTN_SetHighEnableIrq
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine ATTN_SetLowDisableIrq @global
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;
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; @clobbers R16
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ATTN_SetLowDisableIrq:
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.ifdef INT0
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.if COM_IRQ_BIT_ATTN == INT0
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M_IO_READ r16, COM_IRQ_ADDR_ATTN ; disable irq for ATTN line
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cbr r16, (1<<COM_IRQ_BIT_ATTN)
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M_IO_WRITE COM_IRQ_ADDR_ATTN, r16
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.endif
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.endif
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sbi COM_ATTN_DDR, COM_ATTN_PIN ; set ATTN as output
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cbi COM_ATTN_OUTPUT, COM_ATTN_PIN ; set ATTN low
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine ATTN_SetHighEnableIrq @global
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;
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; @clobbers R16
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ATTN_SetHighEnableIrq:
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cbi COM_ATTN_DDR, COM_ATTN_PIN ; set ATTN as input
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.ifdef COM_ATTN_PUE
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cbi COM_ATTN_PUE, COM_ATTN_PIN ; disable pullup on ATTN
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.else
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cbi COM_ATTN_OUTPUT, COM_ATTN_PIN ; disable pullup on ATTN
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.endif
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.ifdef INT0
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.if COM_IRQ_BIT_ATTN == INT0
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M_IO_READ r16, COM_IRQ_ADDR_ATTN ; enable irq for ATTN line
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sbr r16, (1<<COM_IRQ_BIT_ATTN)
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M_IO_WRITE COM_IRQ_ADDR_ATTN, r16
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.endif
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.endif
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine ATTN_IsHigh @global
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;
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; @return CFLAG set if ATTN is high
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; @clobbers none
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ATTN_IsHigh:
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clc
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sbic COM_ATTN_INPUT, COM_ATTN_PIN ; ATTN low?
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sec ; yes, set CF
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ret
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; @end
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@@ -85,6 +85,7 @@ UART_HW_Interface_SetWriteBuffer:
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; ---------------------------------------------------------------------------
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; @routine UART_HW_Interface_EnsureReadBuffer
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;
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; @return CFLAG set if okay, cleared on error
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; @clobbers R16 (R17, R24, R25, X)
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UART_HW_Interface_EnsureReadBuffer:
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@@ -86,6 +86,7 @@
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M_IO_READ r16, UCSR@0A
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cbr r16, (1<<TXC@0) ; clear TXCn interrupt
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M_IO_WRITE UCSR@0A, r16
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M_IO_READ r16, UCSR@0B
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sbr r16, (1<<UDRIE@0) | (1<<TXC@0) | (1<<TXEN@0) ; enable TX UDRE and TXC1 interrupt, enable transceive
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M_IO_WRITE UCSR@0B, r16
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@@ -207,6 +208,9 @@ l_msgFinished_%:
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ldi r17, UART_HW_READMODE_MSGRECEIVED
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rjmp l_incCounterAndEnterMode_%
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l_hwerr_%:
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sbrc r16, DOR ; (1<<FE@0) | (1<<DOR@0) | (1<<UPE@0)
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rjmp DEBUG2
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ldi r16, NET_IFACE_OFFS_ERR_IO_LOW
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rjmp l_incCounterAndEnterSkipping_%
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l_econtent_%:
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@@ -227,6 +231,90 @@ l_end_%:
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; ---------------------------------------------------------------------------
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; @macro M_UART_HW_Uart_EnterReceivedChar
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;
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; @param %0 UART number ("0" for UART0)
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; @param r16 received char
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; @param Y pointer to interface data in SRAM
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; @clobbers R16 (R17, R18, R24, R25, X)
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.macro M_UART_HW_Uart_EnterReceivedChar
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; check read mode
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ldd r17, Y+UART_HW_IFACE_OFFS_READMODE
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cpi r17, UART_HW_READMODE_READING
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breq l_storeChar_%
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cpi r17, UART_HW_READMODE_SKIPPING
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breq l_skipChar_%
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rjmp l_overrun_% ; neither read nor skip mode
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l_skipChar_%:
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clr r16
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std Y+NET_IFACE_OFFS_READTIMER, r16 ; reset read timer
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rjmp l_end_%
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l_storeChar_%:
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mov r18, r16 ; r18=received char
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; check buffer
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ldd r16, Y+UART_HW_IFACE_OFFS_READBUFNUM
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cpi r16, 0xff
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breq l_overrun_%
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; check for buffer overrun
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ldd r17, Y+UART_HW_IFACE_OFFS_READBUFLEFT ; r17=bytes left
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tst r17
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breq l_econtent_% ; msg too long
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; actually store byte, increment/decrement counters and pos
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ldd xl, Y+UART_HW_IFACE_OFFS_READBUFPOS_LOW
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ldd xh, Y+UART_HW_IFACE_OFFS_READBUFPOS_HIGH
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st X+, r18 ; r18=byte to store
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clr r16
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std Y+NET_IFACE_OFFS_READTIMER, r16 ; reset read timer
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std Y+UART_HW_IFACE_OFFS_READBUFPOS_LOW, xl
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std Y+UART_HW_IFACE_OFFS_READBUFPOS_HIGH, xh
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ldd r18, Y+UART_HW_IFACE_OFFS_READBUFUSED ; r18=bytes in buffer
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inc r18
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std Y+UART_HW_IFACE_OFFS_READBUFUSED, r18
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dec r17
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std Y+UART_HW_IFACE_OFFS_READBUFLEFT, r17
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breq l_msgFinished_%
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; check msg size
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cpi r18, 2 ; bytes in buffer, exactly 2?
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brne l_end_% ; nope, done
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sbiw xh:xl, 1 ; yes, determine message length (msgLen at previous pos)
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ld r16, X+ ; read payload length byte
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inc r16 ; + dest addr
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inc r16 ; + msg length
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inc r16 ; + CRC byte
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cpi r16, (NET_BUFFERS_SIZE-2) ; total msg length ok? (subtract 1 for buffer header byte)
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brcc l_econtent_% ; content error (msg too long)
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subi r16, 2 ; subtract bytes already received
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std Y+UART_HW_IFACE_OFFS_READBUFLEFT, r16 ; set new number of bytes left
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brne l_end_% ; jmp if still bytes left to receive
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l_msgFinished_%:
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M_UART_HW_Uart_StopRx @0 ; (R16)
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ldi r16, NET_IFACE_OFFS_PACKETSIN_LOW
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ldi r17, UART_HW_READMODE_MSGRECEIVED
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rjmp l_incCounterAndEnterMode_%
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l_econtent_%:
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ldi r16, NET_IFACE_OFFS_ERR_CONTENT_LOW
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rjmp l_incCounterAndEnterSkipping_%
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l_overrun_%:
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ldi r16, NET_IFACE_OFFS_ERR_NOBUF_LOW
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l_incCounterAndEnterSkipping_%:
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M_UART_HW_Uart_StopRx @0 ; (R16)
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ldi r17, UART_HW_READMODE_SKIPPING
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l_incCounterAndEnterMode_%:
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rcall NET_Interface_IncCounter16 ; (R24, R25)
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std Y+UART_HW_IFACE_OFFS_READMODE, r17 ; set read mode
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l_end_%:
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.endmacro
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; @end
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; ---------------------------------------------------------------------------
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; @macro M_UART_HW_Uart_RxCharFullDuplexIsr
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;
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240
avr/modules/uart_hw/net_uart.asm
Normal file
240
avr/modules/uart_hw/net_uart.asm
Normal file
@@ -0,0 +1,240 @@
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; ***************************************************************************
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; copyright : (C) 2025 by Martin Preuss
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; email : martin@libchipcard.de
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;
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; ***************************************************************************
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; * This file is part of the project "AqHome". *
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; * Please see toplevel file COPYING of that project for license details. *
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; ***************************************************************************
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; ***************************************************************************
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; defines
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.equ NET_UART_MSG_INTERVAL = 1
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; ***************************************************************************
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; data
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.dseg
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netUartIface: .byte UART_HW_IFACE_SIZE
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; ***************************************************************************
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; code
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.cseg
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; ---------------------------------------------------------------------------
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; @routine ComOnUart0_Init @global
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;
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NET_Uart_Init:
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ldi yl, LOW(netUartIface)
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ldi yh, HIGH(netUartIface)
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rcall UART_HW_Interface_Init
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rcall UART_Init
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rcall ATTN_Init
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine NET_Uart_Run @global
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;
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; @clobbers all
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NET_Uart_Run:
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push r15
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in r15, SREG
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cli
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ldi yl, LOW(netUartIface)
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ldi yh, HIGH(netUartIface)
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rcall netUartRunReadModes
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ldd r16, Y+UART_HW_IFACE_OFFS_READMODE ; test for active read mode
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cpi r16, UART_HW_READMODE_IDLE
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brne NET_Uart_Run_end
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rcall netUartRunWriteModes ; only call write routine if read idle
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NET_Uart_Run_end:
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pop r15
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out SREG, r15
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine NET_Uart_Periodically
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;
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; @clobbers all, !Y
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NET_Uart_Periodically:
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ldi yl, LOW(netUartIface)
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ldi yh, HIGH(netUartIface)
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rjmp NET_Interface_Periodically
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; @end
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; ---------------------------------------------------------------------------
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; @routine netUartRunWriteModes
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;
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; @clobbers all, !Y
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netUartRunWriteModes:
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ldd r16, Y+UART_HW_IFACE_OFFS_WRITEMODE ; handle write functions
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cpi r16, UART_HW_WRITEMODE_IDLE
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breq netUartRunWriteIdle
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cpi r16, UART_HW_WRITEMODE_WRITING
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breq netUartRunWriting
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cpi r16, UART_HW_WRITEMODE_WAITBUFFEREMPTY
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breq netUartRunWaitBufferEmpty
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cpi r16, UART_HW_WRITEMODE_WRITEBUFFEREMPTY
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breq netUartRunWriteBufferEmpty
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ret
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; @end
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netUartRunWaitBufferEmpty:
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rcall UART_GetFlags ; (none)
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ldi r17, (1<<UART_FLAGS_LASTBYTESENT_BIT) | (1<<UART_FLAGS_SWUNDERRUN_BIT)
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eor r16, r17
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andi r16, (1<<UART_FLAGS_LASTBYTESENT_BIT) | (1<<UART_FLAGS_SWUNDERRUN_BIT)
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brne netUartRunWaitBufferEmpty_end
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rcall UART_StopTx
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ldi r16, UART_HW_WRITEMODE_WRITEBUFFEREMPTY
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std Y+UART_HW_IFACE_OFFS_WRITEMODE, r16
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rjmp netUartRunWriteBufferEmpty ; we just entered new write mode
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netUartRunWaitBufferEmpty_end:
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ret
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; @end
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netUartRunWriteBufferEmpty:
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ldd r16, Y+UART_HW_IFACE_OFFS_WRITEBUFNUM
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rcall NET_Buffer_ReleaseByNum ; (R16, X)
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ldi r16, 0xff
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std Y+UART_HW_IFACE_OFFS_WRITEBUFNUM, r16
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rcall ATTN_SetHighEnableIrq ; release bus
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ldi r16, UART_HW_WRITEMODE_IDLE
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std Y+UART_HW_IFACE_OFFS_WRITEMODE, r16
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ret
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; @end
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netUartRunWriteIdle:
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ldd r16, Y+NET_IFACE_OFFS_WRITETIMER
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cpi r16, NET_UART_MSG_INTERVAL ; wait a bit between messages
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brcs netUartRunWriteIdle_end
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rcall NET_Interface_PeekNextOutgoingMsgNum ; r16=msgNum
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brcc netUartRunWriteIdle_end ; no outmsg in queue
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rcall ATTN_IsHigh
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brcc netUartRunWriteIdle_end ; ATTN low, jmp
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mov r17, r16
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rcall ATTN_SetLowDisableIrq ; reserve bus as soon as possible (R16)
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Utils_WaitNanoSecs COM_BIT_LENGTH, 0, r22 ; wait for one bit duration
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Utils_WaitNanoSecs COM_BIT_LENGTH, 0, r22 ; wait for one bit duration
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mov r16, r17
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rcall NET_Buffer_Locate ; (R17)
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rcall UART_HW_Interface_SetWriteBuffer
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ldi r17, UART_HW_WRITEMODE_WRITING
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std Y+UART_HW_IFACE_OFFS_WRITEMODE, r17
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rcall NET_Interface_GetNextOutgoingMsgNum ; take msg from queue (R17, R18, X)
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rjmp netUartRunWriting ; just entered writing mode
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netUartRunWriteIdle_end:
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ret
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; @end
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netUartRunWriting:
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ldd r19, Y+UART_HW_IFACE_OFFS_WRITEBUFLEFT
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tst r19
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breq netUartRunWriting_checkTxEn
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rcall UART_GetFlags ; r16=flags (none)
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andi r16, (1<<UART_FLAGS_SWUNDERRUN_BIT) | (1<<UART_FLAGS_LASTBYTESENT_BIT)
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brne netUartRunWriting_error ; got an error while still bytes to send
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push yl
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push yh
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push zl
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push zh
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ldd zl, Y+UART_HW_IFACE_OFFS_WRITEBUFPOS_LOW
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ldd zh, Y+UART_HW_IFACE_OFFS_WRITEBUFPOS_HIGH
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clr r16
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std Y+NET_IFACE_OFFS_WRITETIMER, r16
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netUartRunWriting_loop:
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ld r16, Z
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rcall UART_WriteByte ; (R17, R18, X, Y)
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brcc netUartRunWriting_loopEnd
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adiw zh:zl, 1
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dec r19
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brne netUartRunWriting_loop
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netUartRunWriting_loopEnd:
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pop zl
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pop zh
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pop yh
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pop yl
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std Y+UART_HW_IFACE_OFFS_WRITEBUFPOS_LOW, zl
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std Y+UART_HW_IFACE_OFFS_WRITEBUFPOS_HIGH, zh
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std Y+UART_HW_IFACE_OFFS_WRITEBUFLEFT, r19
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netUartRunWriting_checkTxEn:
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rcall UART_GetFlags ; (none)
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sbrs r16, UART_FLAGS_TXEN_BIT
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rcall UART_StartTx ; (R16)
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tst r19
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brne netUartRunWriting_end
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ldi r16, UART_HW_WRITEMODE_WAITBUFFEREMPTY
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std Y+UART_HW_IFACE_OFFS_WRITEMODE, r16
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rjmp netUartRunWaitBufferEmpty ; we just entered new write mode
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netUartRunWriting_error:
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ldi r16, NET_IFACE_OFFS_ERR_BUSY_LOW
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rcall netUartAbortTx
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netUartRunWriting_end:
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine netUartAbortTx
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;
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; @clobbers all, !Y
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netUartAbortTx:
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rcall NET_Interface_IncCounter16
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rcall UART_StopTx
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rcall UART_ResetWriteBuffer
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rcall ATTN_SetHighEnableIrq
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ldi r16, UART_HW_WRITEMODE_IDLE
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std Y+UART_HW_IFACE_OFFS_WRITEMODE, r16
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ldi r17, 0xff
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ldd r16, Y+UART_HW_IFACE_OFFS_WRITEBUFNUM
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std Y+UART_HW_IFACE_OFFS_WRITEBUFNUM, r17
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rjmp NET_Buffer_ReleaseByNum
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; @end
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netUartRunReadModes:
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ret
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; @end
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398
avr/modules/uart_hw/uart.asm
Normal file
398
avr/modules/uart_hw/uart.asm
Normal file
@@ -0,0 +1,398 @@
|
||||
; ***************************************************************************
|
||||
; copyright : (C) 2025 by Martin Preuss
|
||||
; email : martin@libchipcard.de
|
||||
;
|
||||
; ***************************************************************************
|
||||
; * This file is part of the project "AqHome". *
|
||||
; * Please see toplevel file COPYING of that project for license details. *
|
||||
; ***************************************************************************
|
||||
|
||||
|
||||
; ***************************************************************************
|
||||
; defines
|
||||
|
||||
|
||||
.equ UART_RINGBUFFER_IN_SIZE = 24
|
||||
.equ UART_RINGBUFFER_OUT_SIZE = 24
|
||||
|
||||
|
||||
.equ UART_FLAGS_TXEN_BIT = 7
|
||||
.equ UART_FLAGS_RXEN_BIT = 6
|
||||
.equ UART_FLAGS_HWOVERRUN_BIT = 5
|
||||
.equ UART_FLAGS_FRAMEERROR_BIT = 4
|
||||
.equ UART_FLAGS_SWOVERRUN_BIT = 3
|
||||
.equ UART_FLAGS_SWUNDERRUN_BIT = 2
|
||||
.equ UART_FLAGS_LASTBYTESENT_BIT = 1
|
||||
|
||||
|
||||
|
||||
; ***************************************************************************
|
||||
; data
|
||||
|
||||
.dseg
|
||||
|
||||
uartFlags: .byte 1
|
||||
uartRingbufferIn: .byte RINGBUFFERY_SIZE+UART_RINGBUFFER_IN_SIZE
|
||||
uartRingbufferOut: .byte RINGBUFFERY_SIZE+UART_RINGBUFFER_OUT_SIZE
|
||||
|
||||
|
||||
; ***************************************************************************
|
||||
; code
|
||||
|
||||
.cseg
|
||||
|
||||
|
||||
|
||||
UART_Init:
|
||||
clr r16
|
||||
sts uartFlags, r16
|
||||
|
||||
ldi r16, UART_RINGBUFFER_IN_SIZE
|
||||
ldi yl, LOW(uartRingbufferIn)
|
||||
ldi yh, HIGH(uartRingbufferIn)
|
||||
rcall RingBufferY_Init
|
||||
|
||||
ldi r16, UART_RINGBUFFER_OUT_SIZE
|
||||
ldi yl, LOW(uartRingbufferOut)
|
||||
ldi yh, HIGH(uartRingbufferOut)
|
||||
rcall RingBufferY_Init
|
||||
|
||||
; set baudrate
|
||||
.if clock == 8000000
|
||||
ldi r16, 25 ; (19.2Kb/s at 8MHz)
|
||||
ldi r17, 0
|
||||
.endif
|
||||
|
||||
.if clock == 1000000
|
||||
ldi r16, 2 ; (19.2Kb/s at 1MHz)
|
||||
ldi r17, 0
|
||||
.endif
|
||||
|
||||
M_IO_WRITE UBRRH, r17
|
||||
M_IO_WRITE UBRRL, r16
|
||||
|
||||
; set character format
|
||||
.ifdef URSEL
|
||||
ldi r16, (1<<URSEL) | (1<<USBS) | (1<<UCSZ1) | (1<<UCSZ0)
|
||||
.else
|
||||
ldi r16, (1<<USBS) | (1<<UCSZ1) | (1<<UCSZ0)
|
||||
.endif
|
||||
M_IO_WRITE UCSRC, r16
|
||||
|
||||
ret
|
||||
; @end
|
||||
|
||||
|
||||
|
||||
; ---------------------------------------------------------------------------
|
||||
; @routine UART_StartRx @global
|
||||
;
|
||||
; @clobbers R16
|
||||
|
||||
UART_StartRx:
|
||||
; clear read error flags
|
||||
lds r16, uartFlags
|
||||
cbr r16, (1<<UART_FLAGS_HWOVERRUN_BIT) | (1<<UART_FLAGS_FRAMEERROR_BIT) | (1<<UART_FLAGS_SWOVERRUN_BIT)
|
||||
sbr r16, (1<<UART_FLAGS_RXEN_BIT)
|
||||
sts uartFlags, r16
|
||||
|
||||
M_IO_READ r16, UCSRA ; clear errors
|
||||
cbr r16,(1<<RXC) | (1<<FE) | (1<<DOR) | (1<<UPE)
|
||||
M_IO_WRITE UCSRA, r16
|
||||
|
||||
M_IO_READ r16, UCSRB
|
||||
sbr r16, (1<<RXCIE) | (1<<RXEN) ; enable RX complete interrupt, enable receive
|
||||
M_IO_WRITE UCSRB, r16
|
||||
|
||||
ret
|
||||
; @end
|
||||
|
||||
|
||||
|
||||
; ---------------------------------------------------------------------------
|
||||
; @routine UART_StopRx @global
|
||||
;
|
||||
; @clobbers R16
|
||||
|
||||
UART_StopRx:
|
||||
lds r16, uartFlags
|
||||
cbr r16, (1<<UART_FLAGS_RXEN_BIT)
|
||||
sts uartFlags, r16
|
||||
|
||||
M_IO_READ r16, UCSRB
|
||||
cbr r16, (1<<RXCIE | (1<<RXEN)) ; disable RX complete interrupt, disable receive
|
||||
M_IO_WRITE UCSRB, r16
|
||||
ret
|
||||
; @end
|
||||
|
||||
|
||||
|
||||
; ---------------------------------------------------------------------------
|
||||
; @routine UART_StartTx @global
|
||||
;
|
||||
; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_STATE)
|
||||
; @clobbers R16
|
||||
|
||||
UART_StartTx:
|
||||
; clear write error flags
|
||||
lds r16, uartFlags
|
||||
cbr r16, (1<<UART_FLAGS_SWUNDERRUN_BIT) | (1<<UART_FLAGS_LASTBYTESENT_BIT)
|
||||
sbr r16, (1<<UART_FLAGS_TXEN_BIT)
|
||||
sts uartFlags, r16
|
||||
|
||||
M_IO_READ r16, UCSRA
|
||||
cbr r16, (1<<TXC) ; clear TXC interrupt
|
||||
M_IO_WRITE UCSRA, r16
|
||||
|
||||
M_IO_READ r16, UCSRB
|
||||
sbr r16, (1<<UDRIE) | (1<<TXC) | (1<<TXEN) ; enable TX UDRE and TXC1 interrupt, enable transceive
|
||||
M_IO_WRITE UCSRB, r16
|
||||
|
||||
ret
|
||||
; @end
|
||||
|
||||
|
||||
|
||||
; ---------------------------------------------------------------------------
|
||||
; @routine UART_StopTx @global
|
||||
;
|
||||
; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_STATE)
|
||||
; @clobbers R16
|
||||
|
||||
UART_StopTx:
|
||||
lds r16, uartFlags
|
||||
cbr r16, (1<<UART_FLAGS_TXEN_BIT)
|
||||
sts uartFlags, r16
|
||||
|
||||
M_IO_READ r16, UCSRB
|
||||
cbr r16, (1<<UDRIE) | (1<<TXC) | (1<<TXEN) ; disable TX UDRE and TXC1 interrupt, enable transceive
|
||||
M_IO_WRITE UCSRB, r16
|
||||
|
||||
ret
|
||||
; @end
|
||||
|
||||
|
||||
|
||||
; ---------------------------------------------------------------------------
|
||||
; @routine UART_ReadByte @global
|
||||
;
|
||||
; @return CFLAG on success, cleared on error
|
||||
; @return r16 byte read
|
||||
; @clobbers (R17, R18, X, Y)
|
||||
|
||||
UART_ReadByte:
|
||||
ldi yl, LOW(uartRingbufferIn)
|
||||
ldi yh, HIGH(uartRingbufferIn)
|
||||
rjmp RingBufferY_ReadByteGuarded ; (R17, R18, X)
|
||||
; @end
|
||||
|
||||
|
||||
|
||||
; ---------------------------------------------------------------------------
|
||||
; @routine UART_WriteByte @global
|
||||
;
|
||||
; @clobbers (R17, R18, X, Y)
|
||||
|
||||
UART_WriteByte:
|
||||
ldi yl, LOW(uartRingbufferOut)
|
||||
ldi yh, HIGH(uartRingbufferOut)
|
||||
rjmp RingBufferY_WriteByteGuarded ; (R17, R18, X)
|
||||
; @end
|
||||
|
||||
|
||||
|
||||
; ---------------------------------------------------------------------------
|
||||
; @routine UART_ResetWriteBuffer @global
|
||||
;
|
||||
; @clobbers (R17)
|
||||
|
||||
UART_ResetWriteBuffer:
|
||||
ldi yl, LOW(uartRingbufferOut)
|
||||
ldi yh, HIGH(uartRingbufferOut)
|
||||
rjmp RingBufferY_Reset ; (R17)
|
||||
; @end
|
||||
|
||||
|
||||
|
||||
; ---------------------------------------------------------------------------
|
||||
; @routine UART_GetFlags @global
|
||||
;
|
||||
; @return r16 flags
|
||||
; @clobbers none
|
||||
|
||||
UART_GetFlags:
|
||||
lds r16, uartFlags
|
||||
ret
|
||||
; @end
|
||||
|
||||
|
||||
|
||||
; ---------------------------------------------------------------------------
|
||||
; @routine UART_RxCharIsr @isr
|
||||
;
|
||||
|
||||
UART_RxCharIsr:
|
||||
push r15
|
||||
in r15, SREG
|
||||
push r16
|
||||
push r17
|
||||
push r18
|
||||
push xl
|
||||
push xh
|
||||
push yl
|
||||
push yh
|
||||
rcall uartHandleRxChar
|
||||
pop yh
|
||||
pop yl
|
||||
pop xh
|
||||
pop xl
|
||||
pop r18
|
||||
pop r17
|
||||
pop r16
|
||||
out SREG, r15
|
||||
pop r15
|
||||
reti
|
||||
; @end
|
||||
|
||||
|
||||
|
||||
; ---------------------------------------------------------------------------
|
||||
; @routine UART_TxCharIsr @isr
|
||||
;
|
||||
|
||||
UART_TxCharIsr:
|
||||
push r15
|
||||
in r15, SREG
|
||||
push r16
|
||||
rcall uartHandleTxChar ; (R16)
|
||||
pop r16
|
||||
out SREG, r15
|
||||
pop r15
|
||||
reti
|
||||
; @end
|
||||
|
||||
|
||||
|
||||
; ---------------------------------------------------------------------------
|
||||
; @routine UART_UdreIsr @isr
|
||||
;
|
||||
|
||||
UART_UdreIsr:
|
||||
push r15
|
||||
in r15, SREG
|
||||
push r16
|
||||
push r17
|
||||
push r18
|
||||
push xl
|
||||
push xh
|
||||
push yl
|
||||
push yh
|
||||
rcall uartHandleUdre
|
||||
pop yh
|
||||
pop yl
|
||||
pop xh
|
||||
pop xl
|
||||
pop r18
|
||||
pop r17
|
||||
pop r16
|
||||
out SREG, r15
|
||||
pop r15
|
||||
reti
|
||||
; @end
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
; ---------------------------------------------------------------------------
|
||||
; @routine uartHandleRxChar
|
||||
;
|
||||
; @clobbers R16, R17, Y (R18, X)
|
||||
|
||||
uartHandleRxChar:
|
||||
; check for errors
|
||||
M_IO_READ r16, UCSRA
|
||||
sbrc r16, FE
|
||||
rjmp uartHandleRxChar_hwErrFe
|
||||
sbrc r16, DOR
|
||||
rjmp uartHandleRxChar_hwErrDor
|
||||
; have char?
|
||||
sbrs r16, RXC
|
||||
rjmp uartHandleRxChar_end ; no data
|
||||
|
||||
; read char
|
||||
M_IO_READ r16, UDR ; r16=received char
|
||||
|
||||
ldi yl, LOW(uartRingbufferIn)
|
||||
ldi yh, HIGH(uartRingbufferIn)
|
||||
rcall RingBufferY_WriteByte ; (R17, R18, X)
|
||||
brcs uartHandleRxChar_end
|
||||
lds r16, UART_FLAGS_SWOVERRUN_BIT
|
||||
rjmp uartHandleRxChar_storeErrorFlags
|
||||
uartHandleRxChar_hwErrFe:
|
||||
lds r16, UART_FLAGS_FRAMEERROR_BIT
|
||||
rjmp uartHandleRxChar_storeErrorFlags
|
||||
uartHandleRxChar_hwErrDor:
|
||||
lds r16, UART_FLAGS_HWOVERRUN_BIT
|
||||
rjmp uartHandleRxChar_storeErrorFlags
|
||||
uartHandleRxChar_storeErrorFlags:
|
||||
lds r17, uartFlags
|
||||
or r17, r16
|
||||
sts uartFlags, r17
|
||||
uartHandleRxChar_end:
|
||||
ret
|
||||
; @end
|
||||
|
||||
|
||||
|
||||
; ---------------------------------------------------------------------------
|
||||
; @routine uartHandleUdre
|
||||
;
|
||||
; @clobbers R16, Y (R17, R18, X)
|
||||
|
||||
uartHandleUdre:
|
||||
M_IO_READ r16, UCSRA
|
||||
sbrs r16, UDRE
|
||||
; rjmp uartHandleUdre_disableUdre ; not ready, SNH!
|
||||
rjmp uartHandleUdre_end ; not ready, SNH!
|
||||
ldi yl, LOW(uartRingbufferOut)
|
||||
ldi yh, HIGH(uartRingbufferOut)
|
||||
rcall RingBufferY_ReadByte ; (R17, R18, X)
|
||||
brcc uartHandleUdre_underrun
|
||||
M_IO_WRITE UDR, r16
|
||||
rjmp uartHandleUdre_end
|
||||
uartHandleUdre_underrun:
|
||||
lds r16, uartFlags
|
||||
sbr r16, (1<<UART_FLAGS_SWUNDERRUN_BIT)
|
||||
sts uartFlags, r16
|
||||
uartHandleUdre_disableUdre:
|
||||
M_IO_READ r16, UCSRB
|
||||
cbr r16, (1<<UDRIE) ; disable TX UDRE interrupt
|
||||
M_IO_WRITE UCSRB, r16
|
||||
uartHandleUdre_end:
|
||||
ret
|
||||
; @end
|
||||
|
||||
|
||||
|
||||
; ---------------------------------------------------------------------------
|
||||
; @routine uartHandleTxChar
|
||||
;
|
||||
; @clobbers R16
|
||||
|
||||
uartHandleTxChar:
|
||||
lds r16, uartFlags
|
||||
sbr r16, (1<<UART_FLAGS_LASTBYTESENT_BIT)
|
||||
sts uartFlags, r16
|
||||
|
||||
M_IO_READ r16, UCSRB
|
||||
cbr r16, (1<<TXC) ; disable TXC interrupt
|
||||
M_IO_WRITE UCSRB, r16
|
||||
|
||||
ret
|
||||
; @end
|
||||
|
||||
|
||||
|
||||
|
||||
Reference in New Issue
Block a user