diff --git a/avr/modules/flash/io_bitbang.asm b/avr/modules/flash/io_bitbang.asm index 48b42e7..16999a0 100644 --- a/avr/modules/flash/io_bitbang.asm +++ b/avr/modules/flash/io_bitbang.asm @@ -101,14 +101,14 @@ ioRawInit: ioRawSendMsg: ioRawSendMsg_loop: ldi r16, 0xff ; expect ATTN high - ldi r17, 3 - rcall ioWaitForAttnState100ms ; wait for up to 300ms + ldi r17, 10 + rcall ioWaitForAttnState100ms ; wait for up to 1s brcs ioRawSendMsg_attnHigh ret ioRawSendMsg_attnHigh: ldi xl, LOW(flashSendBuffer) ldi xh, HIGH(flashSendBuffer) - rcall ioRawSendPacket ; R16, R22 (R17, R21, X) + rcall ioRawSendPacket ; R16, R22 (R17, R21, X) brcc ioRawSendMsg_loop ret ; @end @@ -117,12 +117,21 @@ ioRawSendMsg_attnHigh: ; --------------------------------------------------------------------------- ; @routine ioRawWaitForValidMsg +; ; Wait for valid incoming msg ; +; First waits for ATTN line to go high (released) then wait for ATTN +; line to go low. This way we will only start listening at the beginning of +; a message. +; ; @return CFLAG set if okay (packet received), cleared on error ; @clobbers: r16, r17 (r18, r19, r20, r21, r22, X) ioRawWaitForValidMsg: + ldi r16, 0xff ; expect ATTN high + ldi r17, 100 + rcall ioWaitForAttnState100ms ; wait for up to 10s + brcc ioRawWaitForValidMsg_end ; ATTN not high, exit ldi r16, 0 ; expect ATTN low ldi r17, 100 rcall ioWaitForAttnState100ms ; wait for up to 10s @@ -322,7 +331,7 @@ ioRawAcquireBus: cbi COM_ATTN_OUTPUT, COM_ATTN_PIN ; disable pullup on ATTN nop ; needed to sample current input sbis COM_ATTN_INPUT, COM_ATTN_PIN ; ATTN low? - rjmp ioRawAcquireBus_busy ; jump if it is + rjmp ioRawAcquireBus_busy ; jump if it is sbi COM_ATTN_DDR, COM_ATTN_PIN ; set ATTN as output cbi COM_ATTN_OUTPUT, COM_ATTN_PIN ; set ATTN low sec