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comonuart1: fixed bit names, disable IRQ when starting to write.

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This commit is contained in:
Martin Preuss
2025-07-03 00:16:29 +02:00
parent 548a7634b7
commit bfd0cd77a9
1 changed files with 19 additions and 3 deletions
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22
avr/modules/uart_hw2/comonuart1.asm
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@@ -149,6 +149,22 @@ comOnUart1StartReading:
; @clobbers R16, R17, X, Z (R22, R24, R25)
comOnUart1StartWriting:
push r15
inr r15, SREG
cli
rcall comOnUart1StartWriting_noIrq
brcc comOnUart1StartWriting_clc
outr SREG, r15
pop r15
sec
ret
comOnUart1StartWriting_clc:
outr SREG, r15
pop r15
clc
ret
comOnUart1StartWriting_noIrq:
rcall comOnUart1AcquireAttn ; (R22)
brcc comOnUart1StartWriting_ebusy
; copy buffer
@@ -451,7 +467,7 @@ comOnUart1StartTx:
cbr r16, (1<<TXC1) ; clear TXCn interrupt
outr UCSR1A, r16
inr r16, UCSR1B
sbr r16, (1<<UDRIE1) | (1<<TXC1) | (1<<TXEN1) ; enable TX UDRE and TXC1 interrupt, enable transceive
sbr r16, (1<<UDRIE1) | (1<<TXCIE1) | (1<<TXEN1) ; enable TX UDRE and TXC1 interrupt, enable transceive
outr UCSR1B, r16
ret
; @end
@@ -465,7 +481,7 @@ comOnUart1StartTx:
comOnUart1StopTx:
inr r16, UCSR1B
cbr r16, (1<<UDRIE1) | (1<<TXC1) | (1<<TXEN1) ; disable TX UDRE and TXC1 interrupt, enable transceive
cbr r16, (1<<UDRIE1) | (1<<TXCIE1) | (1<<TXEN1) ; disable TX UDRE and TXC1 interrupt, enable transceive
outr UCSR1B, r16
ret
; @end
@@ -806,7 +822,7 @@ comOnUart1TxUdreIsr_end:
comOnUart1TxCharIsr:
; disable further TXC interrupts
inr r16, UCSR1B
cbr r16, (1<<TXC1) ; disable TXC1 interrupt
cbr r16, (1<<TXCIE1) ; disable TXC1 interrupt
outr UCSR1B, r16
rcall comOnUart1StopTx ; (R16)
ldi r16, UART_HW2_MODE_MSGSENT