avr: introduced network module
this will be the base module for network modules.
This commit is contained in:
@@ -13,11 +13,11 @@
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; @macro M_UART_HW_Uart_Init
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;
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; @param %0 UART number ("0" for UART0)
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; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_STATE)
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; @param Y pointer to interface data in SRAM
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; @clobbers R16, R17, X
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.macro M_UART_HW_Uart_Init
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rcall UART_HW_InterfaceInit
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rcall NET_Interface_Init
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; set baudrate
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.if clock == 8000000
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@@ -75,7 +75,7 @@
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; @macro M_UART_HW_Uart_StartTx
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;
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; @param %0 UART number ("0" for UART0)
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; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_STATE)
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; @param Y pointer to interface data in SRAM
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; @clobbers R16
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.macro M_UART_HW_Uart_StartTx
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@@ -94,7 +94,7 @@
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; @macro M_UART_HW_Uart_StopTx
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;
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; @param %0 UART number ("0" for UART0)
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; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_STATE)
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; @param Y pointer to interface data in SRAM
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; @clobbers R16
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.macro M_UART_HW_Uart_StopTx
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@@ -112,7 +112,7 @@
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; Flush receiption buffer.
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;
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; @param %0 UART number ("0" for UART0)
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; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_MODE)
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; @param Y pointer to interface data in SRAM
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; @clobbers R16
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.macro M_UART_HW_Uart_Flush
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@@ -122,7 +122,7 @@ l_loop_%:
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rjmp l_end_%
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lds r16, UDR@0
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clr r16
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std Y+UART_HW_IFACE_OFFS_READTIMER, r16
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std Y+NET_IFACE_OFFS_READTIMER, r16
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rjmp l_loop_%
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l_end_%:
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.endmacro
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@@ -134,7 +134,7 @@ l_end_%:
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; @macro M_UART_HW_Uart_RxCharIsr
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;
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; @param %0 UART number ("0" for UART0)
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; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_MODE)
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; @param Y pointer to interface data in SRAM
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; @clobbers R16 (R17, R18, X)
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.macro M_UART_HW_Uart_RxCharIsr
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@@ -142,7 +142,7 @@ l_end_%:
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lds r16, UCSR@0A ; check for errors
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andi r16, (1<<FE@0) | (1<<DOR@0) | (1<<UPE@0)
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breq l_recv_% ; no error, receive next char
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ldd r16, Y+UART_HW_IFACE_OFFS_STATUS ; set error status
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ldd r16, Y+NET_IFACE_OFFS_STATUS ; set error status
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ori r16, (1<<UART_HW_STATUS_HWERR_BIT) ; -> HWERR
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rjmp l_setStatusAndEnd_%
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l_recv_%:
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@@ -153,13 +153,13 @@ l_recv_%:
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rcall UART_HW_InterfaceWriteToReadBuffer ; (R17, R18, X)
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brcc l_overrun_%
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clr r16
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std Y+UART_HW_IFACE_OFFS_READTIMER, r16 ; reset read timer
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std Y+NET_IFACE_OFFS_READTIMER, r16 ; reset read timer
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rjmp l_end_%
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l_overrun_%:
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ldd r16, Y+UART_HW_IFACE_OFFS_STATUS ; set overrun error
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ldd r16, Y+NET_IFACE_OFFS_STATUS ; set overrun error
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ori r16, (1<<UART_HW_STATUS_OVERRUN_BIT) ; -> OVERRUN
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l_setStatusAndEnd_%:
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std Y+UART_HW_IFACE_OFFS_STATUS, r16
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std Y+NET_IFACE_OFFS_STATUS, r16
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l_end_%:
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#endif
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.endmacro
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@@ -173,7 +173,7 @@ l_end_%:
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; Handler for UDREn interrupt called when TX data register is empty.
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;
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; @param %0 UART number ("0" for UART0)
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; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_MODE)
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; @param Y pointer to interface data in SRAM
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; @clobbers R16, R17, X
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.macro M_UART_HW_Uart_TxUdreIsr
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@@ -197,18 +197,18 @@ l_end_%:
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breq l_disable_irq_% ; nothing left to write
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; get read ptr, read byte, inc read ptr, store ptr and bytesLeft
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ldd xl, Y+UART_HW_IFACE_OFFS_WRITEBUFPOSLOW
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ldd xh, Y+UART_HW_IFACE_OFFS_WRITEBUFPOSHIGH
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ldd xl, Y+UART_HW_IFACE_OFFS_WRITEBUFPOS_LOW
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ldd xh, Y+UART_HW_IFACE_OFFS_WRITEBUFPOS_HIGH
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ld r16, X+ ; r16=byte to write
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std Y+UART_HW_IFACE_OFFS_WRITEBUFPOSLOW, xl
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std Y+UART_HW_IFACE_OFFS_WRITEBUFPOSHIGH, xh
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std Y+UART_HW_IFACE_OFFS_WRITEBUFPOS_LOW, xl
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std Y+UART_HW_IFACE_OFFS_WRITEBUFPOS_HIGH, xh
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dec r17
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std Y+UART_HW_IFACE_OFFS_WRITEBUFLEFT, r17
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; send byte, reset write timer
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sts UDR@0, r16
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clr r16
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std Y+UART_HW_IFACE_OFFS_WRITETIMER, r16 ; reset write timer
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std Y+NET_IFACE_OFFS_WRITETIMER, r16 ; reset write timer
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; still bytes left to write?
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tst r17
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@@ -234,7 +234,7 @@ l_end_%:
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; the data register is empty.
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;
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; @param %0 UART number ("0" for UART0)
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; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_MODE)
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; @param Y pointer to interface data in SRAM
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; @clobbers R16
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.macro M_UART_HW_Uart_TxCharIsr
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