bmp280: more work on module.

This commit is contained in:
Martin Preuss
2023-01-30 01:01:19 +01:00
parent 8b3a1defd7
commit b4f16dd987

View File

@@ -46,14 +46,7 @@ BMP280_Init:
rcall bmp280ReadId rcall bmp280ReadId
brcc BMP280_Init_error brcc BMP280_Init_error
lds bmp280Id, r16 ; store id sts bmp280Id, r16 ; store id
push r16
rcall bmp280PrintDebug
pop r2 ; pop r16 into r2
ldi r16, 240
mov r1, r16
ldi r16, 0xff
rcall COM_EnqueueDebug
sec sec
ret ret
BMP280_Init_error: BMP280_Init_error:
@@ -87,33 +80,51 @@ BMP280_Fini:
; USED: R15, R16 (R17, R18, R22) ; USED: R15, R16 (R17, R18, R22)
bmp280ReadId: bmp280ReadId:
ldi r16, 0xd0
rjmp bmp280ReadSingleReg
; ---------------------------------------------------------------------------
; bmp280ReadSingleReg
;
; IN:
; - R16: register id
; OUT:
; - CFLAG: set if okay, clear on error
; - R16 : register content
; USED: R1, R15, R16 (R17, R18, R22)
bmp280ReadSingleReg:
in r15, SREG in r15, SREG
cli cli
mov r1, r16
rcall twiStart ; (R22) rcall twiStart ; (R22)
ldi r16, (BMP280_ADDR*2) ; start in write mode ldi r16, (BMP280_ADDR*2) ; start in write mode
rcall twiSendByteExpectAck ; (R16, R17, R18, R22) rcall twiSendByteExpectAck ; (R16, R17, R18, R22)
brcc bmp280ReadId_error brcc bmp280ReadSingleReg_error
ldi r16, 0xd0 ; register "id" mov r16, r1 ; register num
rcall twiSendByteExpectAck ; (R16, R17, R18, R22) rcall twiSendByteExpectAck ; (R16, R17, R18, R22)
brcc bmp280ReadId_error brcc bmp280ReadSingleReg_error
rcall twiRestart ; (R22) rcall twiRestart ; (R22)
ldi r16, (BMP280_ADDR*2)+1 ; restart in read mode ldi r16, (BMP280_ADDR*2)+1 ; restart in read mode
rcall twiSendByteExpectAck ; (R16, R17, R18, R22) rcall twiSendByteExpectAck ; (R16, R17, R18, R22)
brcc bmp280ReadId_error brcc bmp280ReadSingleReg_error
rcall twiReceiveByteSendAck ; read ID rcall twiReceiveByteSendAck ; read ID
brcc bmp280ReadId_error brcc bmp280ReadSingleReg_error
rcall twiStop ; (R22) rcall twiStop ; (R22)
out SREG, r15 out SREG, r15
sec sec
ret ret
bmp280ReadId_error: bmp280ReadSingleReg_error:
rcall twiStop ; (R22) rcall twiStop ; (R22)
out SREG, r15 out SREG, r15
clc clc
ret ret
; --------------------------------------------------------------------------- ; ---------------------------------------------------------------------------
; bmp280ReadRegsToSram ; bmp280ReadRegsToSram
; ;
@@ -146,6 +157,7 @@ bmp280ReadRegsToSram:
bmp280ReadRegsToSram_loop: bmp280ReadRegsToSram_loop:
rcall twiReceiveByteSendAck ; read register content rcall twiReceiveByteSendAck ; read register content
brcc bmp280ReadRegsToSram brcc bmp280ReadRegsToSram
st x+, r16 ; store register content
dec r2 dec r2
brne bmp280ReadRegsToSram_loop brne bmp280ReadRegsToSram_loop
rcall twiStop ; (R22) rcall twiStop ; (R22)
@@ -158,3 +170,6 @@ bmp280ReadRegsToSram_error:
clc clc
ret ret