diff --git a/avr/modules/uart_hw/m_lowlevel_uart.asm b/avr/modules/uart_hw/m_lowlevel_uart.asm
index 1985b1f..6e028c4 100644
--- a/avr/modules/uart_hw/m_lowlevel_uart.asm
+++ b/avr/modules/uart_hw/m_lowlevel_uart.asm
@@ -30,12 +30,16 @@
   ldi r17, 0  
 .endif
 
-  sts UBRR@0H, r17
-  sts UBRR@0L, r16
+  M_IO_WRITE UBRR@0H, r17
+  M_IO_WRITE UBRR@0L, r16
 
   ; set character format 
+.ifdef URSEL
+  ldi r16, (1<<URSEL) | (1<<USBS@0)|(3<<UCSZ@00)
+.else
   ldi r16, (1<<USBS@0)|(3<<UCSZ@00)
-  sts UCSR@0C, r16
+.endif
+  M_IO_WRITE UCSR@0C, r16
 .endmacro
 ; @end
 
@@ -48,9 +52,9 @@
 ; @clobbers none
 
 .macro M_UART_HW_Uart_StartRx
-  lds r16, UCSR@0B
+  M_IO_READ r16, UCSR@0B
   sbr r16, (1<<RXCIE@0) | (1<<RXEN@0)  ; enable RX complete interrupt, enable receive
-  sts UCSR@0B, r16
+  M_IO_WRITE UCSR@0B, r16
 .endmacro
 ; @end
 
@@ -63,9 +67,9 @@
 ; @clobbers R16
 
 .macro M_UART_HW_Uart_StopRx
-  lds r16, UCSR@0B
+  M_IO_READ r16, UCSR@0B
   cbr r16, (1<<RXCIE@0 | (1<<RXEN@0))   ; disable RX complete interrupt, disable receive
-  sts UCSR@0B, r16
+  M_IO_WRITE UCSR@0B, r16
 .endmacro
 ; @end
 
@@ -79,12 +83,12 @@
 ; @clobbers R16
 
 .macro M_UART_HW_Uart_StartTx
-  lds r16, UCSR@0A
+  M_IO_READ r16, UCSR@0A
   cbr r16, (1<<TXC@0)                               ; clear TXCn interrupt
-  sts UCSR@0A, r16
-  lds r16, UCSR@0B
+  M_IO_WRITE UCSR@0A, r16
+  M_IO_READ r16, UCSR@0B
   sbr r16, (1<<UDRIE@0) | (1<<TXC@0) | (1<<TXEN@0)  ; enable TX UDRE and TXC1 interrupt, enable transceive
-  sts UCSR@0B, r16
+  M_IO_WRITE UCSR@0B, r16
 .endmacro
 ; @end
 
@@ -98,9 +102,9 @@
 ; @clobbers R16
 
 .macro M_UART_HW_Uart_StopTx
-  lds r16, UCSR@0B
+  M_IO_READ r16, UCSR@0B
   cbr r16, (1<<UDRIE@0) | (1<<TXC@0) | (1<<TXEN@0)  ; disable TX UDRE and TXC1 interrupt, enable transceive
-  sts UCSR@0B, r16
+  M_IO_WRITE UCSR@0B, r16
 .endmacro
 ; @end
 
@@ -117,10 +121,10 @@
 
 .macro M_UART_HW_Uart_Flush
 l_loop_%:
-    lds r16, UCSR@0A
+    M_IO_READ r16, UCSR@0A
     sbrs r16, RXC@0
       rjmp l_end_%
-    lds r16, USART@0_DATAREG
+    M_IO_READ r16, USART@0_DATAREG
     clr r16
     std Y+NET_IFACE_OFFS_READTIMER, r16
   rjmp l_loop_%
@@ -139,14 +143,14 @@ l_end_%:
 
 .macro M_UART_HW_Uart_RxCharHalfDuplexIsr
   ; check for errors
-  lds r16, UCSR@0A                              ; check for errors
+  M_IO_READ r16, UCSR@0A                              ; check for errors
   andi r16, (1<<FE@0) | (1<<DOR@0) | (1<<UPE@0)
   brne l_hwerr_%
   ; read char
-  lds r16, UCSR@0A
+  M_IO_READ r16, UCSR@0A
   sbrs r16, RXC@0
     rjmp l_end_%                                ; no data
-  lds r16, USART@0_DATAREG                                ; r16=received char
+  M_IO_READ r16, USART@0_DATAREG                                ; r16=received char
   ; check read mode
   ldd r17, Y+UART_HW_IFACE_OFFS_READMODE
   cpi r17, UART_HW_READMODE_READING
@@ -232,14 +236,14 @@ l_end_%:
 
 .macro M_UART_HW_Uart_RxCharFullDuplexIsr
   ; check for errors
-  lds r16, UCSR@0A                              ; check for errors
+  M_IO_READ r16, UCSR@0A                              ; check for errors
   andi r16, (1<<FE@0) | (1<<DOR@0) | (1<<UPE@0)
   brne l_hwerr_%
   ; read char
-  lds r16, UCSR@0A
+  M_IO_READ r16, UCSR@0A
   sbrs r16, RXC@0
     rjmp l_end_%                                ; no data
-  lds r16, USART@0_DATAREG                                ; r16=received char
+  M_IO_READ r16, USART@0_DATAREG                                ; r16=received char
   ; check read mode
   ldd r17, Y+UART_HW_IFACE_OFFS_READMODE
   cpi r17, UART_HW_READMODE_READING
@@ -326,7 +330,7 @@ l_end_%:
 ; @clobbers R16, R17, X
 
 .macro M_UART_HW_Uart_TxUdreIsr
-  lds r16, UCSR@0A
+  M_IO_READ r16, UCSR@0A
   sbrs r16,UDRE@0
     rjmp l_disable_irq_%                       ; not ready
 
@@ -355,7 +359,7 @@ l_end_%:
   std Y+UART_HW_IFACE_OFFS_WRITEBUFLEFT, r17
   
   ; send byte, reset write timer
-  sts USART@0_DATAREG, r16
+  M_IO_WRITE USART@0_DATAREG, r16
   clr r16
   std Y+NET_IFACE_OFFS_WRITETIMER, r16     ; reset write timer
   
@@ -367,9 +371,9 @@ l_end_%:
 
 l_disable_irq_%:
   ; disable further DRE1 interrupts
-  lds r16, UCSR@0B
+  M_IO_READ r16, UCSR@0B
   cbr r16, (1<<UDRIE@0)                        ; disable TX data register empty interrupt
-  sts UCSR@0B, r16
+  M_IO_WRITE UCSR@0B, r16
 l_end_%:
 .endmacro
 ; @end
@@ -393,9 +397,9 @@ l_end_%:
   brne l_end_%
 
   ; disable further TXC1 interrupts
-  lds r16, UCSR@0B
+  M_IO_READ r16, UCSR@0B
   cbr r16, (1<<TXC@0)                          ; disable TXC1 interrupt
-  sts UCSR@0B, r16
+  M_IO_WRITE UCSR@0B, r16
 
   ; change write mode to WRITEBUFFEREMPTY
   ldi r16, UART_HW_WRITEMODE_WRITEBUFFEREMPTY