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mainly built-fixes.

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This commit is contained in:
Martin Preuss
2025-01-01 19:33:32 +01:00
parent a7adf15bf6
commit a3d5b33105
71 changed files with 3093 additions and 90 deletions
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14
avr/modules/uart_irq/0BUILD Normal file
View File

@@ -0,0 +1,14 @@
<?xml?>
<gwbuild>
<extradist>
defs.asm
iface.asm
iface1.asm
iface2.asm
</extradist>
</gwbuild>

43
avr/modules/uart_irq/iface.asm
View File

@@ -229,20 +229,17 @@ uart_irq_JumpToStateFunction:
push xh
uart_irq_JumpToStateFunction_end:
ret ; indirect jump to address we just pushed to the stack
; @end
uart_irq_state_jumptable:
rjmp uart_irq_handle_idle
rjmp uart_irq_handle_waitforattnhigh
rjmp uart_irq_handle_waitforstartbit
rjmp uart_irq_handle_waitfordatabit
rjmp uart_irq_handle_waitforstopbit
rjmp uart_irq_handle_sendingattn
rjmp uart_irq_handle_sendingstartbit
rjmp uart_irq_handle_sendingdatabit
rjmp uart_irq_handle_sendingstopbit
rjmp uart_irq_handle_idle ; (R16)
rjmp uart_irq_handle_waitforattnhigh ; (R16)
rjmp uart_irq_handle_waitforstartbit ; (R16)
rjmp uart_irq_handle_waitfordatabit ; (R16)
rjmp uart_irq_handle_waitforstopbit ; (R16, R17, X)
rjmp uart_irq_handle_sendingattn ; (R16)
rjmp uart_irq_handle_sendingstartbit ; (R16, R17, X)
rjmp uart_irq_handle_sendingdatabit ; (R16)
rjmp uart_irq_handle_sendingstopbit ; (R16)
; @end
; ---------------------------------------------------------------------------
@@ -717,13 +714,31 @@ uart_irq_timer_init: ; setup timer for IRQ every 52/4
; Settings for clock 8Mhz
; use timer0 with prescaler 1, OCR0A=104-1 (irq every 13us)
;
.if clock == 8000000
ldi r16, (0<<CS02) | (0<<CS01) | (1<<CS00) ; Prescaler 1
out TCCR0B, r16
; ldi r16, 52-1 ; set timer for 8 times baudrate (fixed to 19200 for now)
ldi r16, 104-1 ; set timer for 4 times baudrate (fixed to 19200 for now)
; ldi r16, 208-1 ; set timer for 2 times baudrate (fixed to 19200 for now)
out OCR0A, r16
.endif
;
; Settings for clock 16Mhz
; use timer0 with prescaler 1, OCR0A=208-1 (irq every 13us)
; alternative: prescaler 8, OCR0A=26-1 (irq every 13us)
;
.if clock == 16000000
ldi r16, (0<<CS02) | (0<<CS01) | (1<<CS00) ; Prescaler 1
out TCCR0B, r16
ldi r16, 208-1 ; set timer for 4 times baudrate (fixed to 19200 for now)
out OCR0A, r16
.endif
ldi r16, (1<<OCF0A) ; clear pending interrupts
.ifdef TIFR0