mainly built-fixes.

avr/modules/0BUILD

@@ -25,6 +25,7 @@
     timer
     twimaster
     uart_bitbang
+    uart_irq
   </subdirs>
 
 </gwbuild>

avr/modules/com2/0BUILD

@@ -6,9 +6,7 @@
     buffer.asm
     crc.asm
     defs.asm
-    lowlevel.asm
     main.asm
-    packets.asm
     screen.asm
   </extradist>
 

avr/modules/flash/flash.asm

@@ -162,10 +162,10 @@ Flash_WritePage:
 ; REGS: R16
 
 flashDoSpm:
-wait:                ; wait for possibly previous SPM to complete
+flashDoSpm_wait:                ; wait for possibly previous SPM to complete
     in r16, SPMCSR
     sbrc r16, SPMEN
-  rjmp wait
+  rjmp flashDoSpm_wait
   ; SPM timed sequence
   out SPMCSR, r20
   spm

avr/modules/uart_bitbang/0BUILD

@@ -3,8 +3,10 @@
 <gwbuild>
 
   <extradist>
-    main.asm
     bytelevel.asm
+    defs.asm
+    main.asm
+    packetlevel.asm
   </extradist>
 
 </gwbuild>

avr/modules/uart_irq/0BUILD

@@ -0,0 +1,14 @@
+<?xml?>
+
+<gwbuild>
+
+  <extradist>
+    defs.asm
+    iface.asm
+    iface1.asm
+    iface2.asm
+  </extradist>
+
+</gwbuild>
+
+

avr/modules/uart_irq/iface.asm

@@ -229,20 +229,17 @@ uart_irq_JumpToStateFunction:
   push xh
 uart_irq_JumpToStateFunction_end:
   ret ; indirect jump to address we just pushed to the stack
-; @end
-
-
-
 uart_irq_state_jumptable:
-  rjmp uart_irq_handle_idle
-  rjmp uart_irq_handle_waitforattnhigh
-  rjmp uart_irq_handle_waitforstartbit
-  rjmp uart_irq_handle_waitfordatabit
-  rjmp uart_irq_handle_waitforstopbit
-  rjmp uart_irq_handle_sendingattn
-  rjmp uart_irq_handle_sendingstartbit
-  rjmp uart_irq_handle_sendingdatabit
-  rjmp uart_irq_handle_sendingstopbit
+  rjmp uart_irq_handle_idle            ; (R16)
+  rjmp uart_irq_handle_waitforattnhigh ; (R16)
+  rjmp uart_irq_handle_waitforstartbit ; (R16)
+  rjmp uart_irq_handle_waitfordatabit  ; (R16)
+  rjmp uart_irq_handle_waitforstopbit  ; (R16, R17, X)
+  rjmp uart_irq_handle_sendingattn     ; (R16)
+  rjmp uart_irq_handle_sendingstartbit ; (R16, R17, X)
+  rjmp uart_irq_handle_sendingdatabit  ; (R16)
+  rjmp uart_irq_handle_sendingstopbit  ; (R16)
+; @end
 
 
 ; ---------------------------------------------------------------------------
@@ -717,13 +714,31 @@ uart_irq_timer_init:                           ; setup timer for IRQ every 52/4
 ; Settings for clock 8Mhz
 ; use timer0 with prescaler 1, OCR0A=104-1 (irq every 13us)
 ;
+.if clock == 8000000
+
   ldi r16, (0<<CS02) | (0<<CS01) | (1<<CS00)  ; Prescaler 1
   out TCCR0B, r16
-
 ;  ldi r16, 52-1                    ; set timer for 8 times baudrate (fixed to 19200 for now)
   ldi r16, 104-1                    ; set timer for 4 times baudrate (fixed to 19200 for now)
 ;  ldi r16, 208-1                   ; set timer for 2 times baudrate (fixed to 19200 for now)
   out OCR0A, r16
+.endif
+
+
+;
+; Settings for clock 16Mhz
+; use timer0 with prescaler 1, OCR0A=208-1 (irq every 13us)
+; alternative:    prescaler 8, OCR0A=26-1  (irq every 13us)
+;
+.if clock == 16000000
+  ldi r16, (0<<CS02) | (0<<CS01) | (1<<CS00)  ; Prescaler 1
+  out TCCR0B, r16
+
+  ldi r16, 208-1                   ; set timer for 4 times baudrate (fixed to 19200 for now)
+  out OCR0A, r16
+.endif
+
+
 
   ldi r16, (1<<OCF0A)             ; clear pending interrupts
 .ifdef TIFR0