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simplified timer and sleep setup code for AtTiny84.

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This commit is contained in:
Martin Preuss
2025-06-01 22:36:59 +02:00
parent c45eb6cca2
commit 9bd3182bd5
1 changed files with 8 additions and 14 deletions
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22
avr/devices/all/hw_tn84.asm
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@@ -72,13 +72,14 @@ systemSleep:
; only modify SE, SM1 and SM0 ; only modify SE, SM1 and SM0
cli cli
in r16, MCUCR in r16, MCUCR
ldi r17, (1<<SE) | (1<<SM1) | (1<<SM0) cbr r16, (1<<SE) | (1<<SM1) | (1<<SM0)
neg r17 out MCUCR, r16
and r16, r17 sbr r16, (1<<SE) | (0<<SM1) | (0<<SM0) ; sleep mode "idle", enable
ori r16, (1<<SE) ; sleep mode "idle", enable
out MCUCR, r16 out MCUCR, r16
sei ; make sure interrupts really are enabled sei ; make sure interrupts really are enabled
sleep ; sleep, wait for interrupt sleep ; sleep, wait for interrupt
cbr r16, (1<<SE) | (1<<SM1) | (1<<SM0)
out MCUCR, r16
ret ret
; @end ; @end
@@ -90,7 +91,7 @@ systemSleep:
; ;
systemSetupTimer0: ; setup timer for IRQ every 100ms systemSetupTimer0: ; setup timer for IRQ every 100ms
ldi r16, (1<<CS02) | (0<<CS01) | (1<<CS00) ; Prescaler 1024 ldi r16, (0<<WGM02) | (1<<CS02) | (0<<CS01) | (1<<CS00) ; Prescaler 1024
out TCCR0B, r16 out TCCR0B, r16
ldi r16, (1<<WGM01) | (0<<WGM00) ; CTC mode ldi r16, (1<<WGM01) | (0<<WGM00) ; CTC mode
@@ -125,19 +126,12 @@ systemSetupTimer0: ; setup timer for IRQ every 100ms
ldi r16, (1<<OCF0A) ; clear pending interrupts ldi r16, (1<<OCF0A) ; clear pending interrupts
.ifdef TIFR0
out TIFR0, r16 out TIFR0, r16
.else
out TIFR, r16
.endif
ldi r16, (1<<OCIE0A) ; Timer/Counter0 Output Compare Match A Interrupt Enable ldi r16, (1<<OCIE0A) ; Timer/Counter0 Output Compare Match A Interrupt Enable
.ifdef TIMSK0
out TIMSK0, r16 out TIMSK0, r16
.else
out TIMSK, r16 sec
.endif
sec
ret ret
; @end ; @end