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renamed makros M_IO_READ and M_IO_WRITE to inr and outr

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This commit is contained in:
Martin Preuss
2025-05-28 00:49:07 +02:00
parent 042db13994
commit 961568f721
6 changed files with 77 additions and 50 deletions
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47
avr/modules/uart_hw/uart.asm
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@@ -38,16 +38,17 @@ UART_Init:
ldi r17, 0
.endif
M_IO_WRITE UBRRH, r17
M_IO_WRITE UBRRL, r16
outr UBRRH, r17
outr UBRRL, r16
; set character format
.ifdef URSEL
ldi r16, (1<<URSEL) | (1<<USBS) | (1<<UCSZ1) | (1<<UCSZ0)
; ldi r16, (1<<URSEL) | (1<<USBS) | (1<<UCSZ1) | (1<<UCSZ0)
ldi r16, (1<<URSEL) | (1<<USBS) | (3<<UCSZ0)
.else
ldi r16, (1<<USBS) | (1<<UCSZ1) | (1<<UCSZ0)
.endif
M_IO_WRITE UCSRC, r16
outr UCSRC, r16
ret
; @end
@@ -69,16 +70,16 @@ UART_SendBytes:
; send bytes
UART_SendBytes_loop1:
M_IO_READ r16, UCSRA
inr r16, UCSRA
sbrs r16, UDRE
rjmp UART_SendBytes_loop1
ld r16, X+
M_IO_WRITE UDR, r16
outr UDR, r16
dec r17
brne UART_SendBytes_loop1
; wait until all data sent
UART_SendBytes_loop2:
M_IO_READ r16, UCSRA
inr r16, UCSRA
sbrs r16, TXC
rjmp UART_SendBytes_loop2
rcall UART_StopTx
@@ -100,7 +101,7 @@ UART_SendBytes_secRet:
UART_RecvPacket:
cpi r17, 3
brcs UART_RecvPacket_invalid
rcall uartRecvByteWithin10ms ; recv destination address
rcall uartRecvByteWithin10ms ; recv destination address (R16)
brcc UART_RecvPacket_ioError
cp r16, r18
breq UART_RecvPacket_forMe
@@ -158,10 +159,10 @@ uartRecvByteWithin10ms:
pop r22
pop r20
brcc uartRecvByteWithin10ms_end
M_IO_READ r16, UCSRA ; check for errors
inr r16, UCSRA ; check for errors
andi r16, (1<<FE) | (1<<DOR)
brne uartRecvByteWithin10ms_error
M_IO_READ r16, UDR ; read data byte
inr r16, UDR ; read data byte
sec
ret
uartRecvByteWithin10ms_error:
@@ -213,7 +214,7 @@ uartWaitForData10ms_gotit:
uartWaitForData1000Cycles:
ldi r20, 140 ; 1
uartWaitForData_loop:
M_IO_READ r22, UCSRA ; 2
inr r22, UCSRA ; 2
sbrc r22, RXC ; 2/3
rjmp uartWaitForData_gotit ; 2
dec r20 ; 1
@@ -235,14 +236,14 @@ uartWaitForData_gotit:
; @clobbers R16
UART_StartRx:
M_IO_READ r16, UCSRA ; clear errors
inr r16, UCSRA ; clear errors
cbr r16, (1<<FE) | (1<<DOR) | (1<<UPE)
sbr r16, (1<<RXC)
M_IO_WRITE UCSRA, r16
outr UCSRA, r16
M_IO_READ r16, UCSRB
inr r16, UCSRB
sbr r16, (1<<RXEN) ; enable receive
M_IO_WRITE UCSRB, r16
outr UCSRB, r16
ret
; @end
@@ -255,9 +256,9 @@ UART_StartRx:
; @clobbers R16
UART_StopRx:
M_IO_READ r16, UCSRB
inr r16, UCSRB
cbr r16, (1<<RXCIE | (1<<RXEN)) ; disable RX complete interrupt, disable receive
M_IO_WRITE UCSRB, r16
outr UCSRB, r16
ret
; @end
@@ -270,13 +271,13 @@ UART_StopRx:
; @clobbers R16
UART_StartTx:
M_IO_READ r16, UCSRA
inr r16, UCSRA
sbr r16, (1<<TXC) ; clear TXC interrupt
M_IO_WRITE UCSRA, r16
outr UCSRA, r16
M_IO_READ r16, UCSRB
inr r16, UCSRB
sbr r16, (1<<TXEN) ; enable transceive
M_IO_WRITE UCSRB, r16
outr UCSRB, r16
ret
; @end
@@ -290,9 +291,9 @@ UART_StartTx:
; @clobbers R16
UART_StopTx:
M_IO_READ r16, UCSRB
inr r16, UCSRB
cbr r16, (1<<UDRIE) | (1<<TXC) | (1<<TXEN) ; disable TX UDRE and TXC1 interrupt, enable transceive
M_IO_WRITE UCSRB, r16
outr UCSRB, r16
ret
; @end