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renamed makros M_IO_READ and M_IO_WRITE to inr and outr

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This commit is contained in:
Martin Preuss
2025-05-28 00:49:07 +02:00
parent 042db13994
commit 961568f721
6 changed files with 77 additions and 50 deletions
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25
avr/common/utils_io.asm
View File

@@ -7,7 +7,7 @@
; * Please see toplevel file COPYING of that project for license details. *
; ***************************************************************************
#if 0
; M_IO_READ DEST, SRC
.macro M_IO_READ
.if @1 < 64
@@ -27,3 +27,26 @@
sts @0, @1
.endif
.endmacro
#endif
; inr DEST, SRC
.macro inr
.if @1 < 64
in @0, @1
.else
lds @0, @1
.endif
.endmacro
; outr DEST, SRC
.macro outr
.if @0 < 64
out @0, @1
.else
sts @0, @1
.endif
.endmacro

24
avr/devices/all/hw_m8515.asm
View File

@@ -69,25 +69,25 @@ systemSleep:
; only modify SE, SM2, SM1 and SM0
cli
M_IO_READ r16, MCUCR
inr r16, MCUCR
cbr r16, (1<<SE) | (1<<SM2) | (1<<SM1)
M_IO_WRITE MCUCR, r16
outr MCUCR, r16
M_IO_READ r16, EMCUCR
inr r16, EMCUCR
cbr r16, (1<<SM0)
M_IO_WRITE EMCUCR, r16
outr EMCUCR, r16
sei ; make sure interrupts really are enabled
M_IO_READ r16, MCUCR ; enable sleep mode
inr r16, MCUCR ; enable sleep mode
sbr r16, (1<<SE)
M_IO_WRITE MCUCR, r16
outr MCUCR, r16
sleep ; sleep, wait for interrupt
M_IO_READ r16, MCUCR ; disable sleep mode
inr r16, MCUCR ; disable sleep mode
cbr r16, (1<<SE)
M_IO_WRITE MCUCR, r16
outr MCUCR, r16
ret
; @end
@@ -140,13 +140,13 @@ systemSetupTimer0: ; setup timer for IRQ every 100ms
.endif
.ifdef TIMSK0
M_IO_READ r16, TIMSK0
inr r16, TIMSK0
sbr r16, (1<<OCIE0) ; Timer/Counter0 Output Compare Match A Interrupt Enable
M_IO_WRITE TIMSK0, r16
outr TIMSK0, r16
.else
M_IO_READ r16, TIMSK
inr r16, TIMSK
sbr r16, (1<<OCIE0) ; Timer/Counter0 Output Compare Match A Interrupt Enable
M_IO_WRITE TIMSK, r16
outr TIMSK, r16
.endif
sec

14
avr/modules/spi_hw/main.asm
View File

@@ -93,13 +93,13 @@ SPIHW_MasterStart:
sbrc r16, SPIHW_MODE_SPEED1_BIT
sbr r17, (1<<SPR1)
sbr r17, (1<<SPE) | (1<<MSTR)
M_IO_WRITE SPCR, r17
outr SPCR, r17
; setup SPSR
clr r17
sbrc r16, SPIHW_MODE_DOUBLESPEED_BIT
sbr r17, (1<<SPI2X)
M_IO_WRITE SPSR, r17
outr SPSR, r17
ret
; @end
@@ -115,9 +115,9 @@ SPIHW_MasterStart:
SPIHW_MasterStop:
; sbi SPIHW_SS_OUTPUT, SPIHW_SS_PIN ; SS high
M_IO_READ r16, SPCR
inr r16, SPCR
cbr r16, (1<<SPE)
M_IO_WRITE SPCR, r16
outr SPCR, r16
ret
; @end
@@ -176,7 +176,7 @@ SPIHW_MasterTransfer:
; @clobbers none
SPIHW_MasterSendByte:
M_IO_WRITE SPDR, r16
outr SPDR, r16
ret
; @end
@@ -191,10 +191,10 @@ SPIHW_MasterSendByte:
; @clobbers none
SPIHW_WaitForTransferComplete:
M_IO_READ r16, SPSR
inr r16, SPSR
sbrs r16, SPIF
rjmp SPIHW_WaitForTransferComplete
M_IO_READ r16, SPDR
inr r16, SPDR
ret
; @end

13
avr/modules/uart_hw/attn.asm
View File

@@ -23,10 +23,13 @@
ATTN_Init:
.ifdef INT0
.if COM_IRQ_BIT_ATTN == INT0
M_IO_READ r16, MCUCR
inr r16, MCUCR
cbr r16, (1<<ISC01) | (1<<ISC00)
sbr r16, (1<<ISC01) | (0<<ISC00) ; falling edge of ATTN
outr MCUCR, r16
; sbr r16, (0<<ISC01) | (0<<ISC00) ; low level triggers
.endif
.endif
rcall ATTN_SetHighEnableIrq
@@ -44,9 +47,9 @@ ATTN_Init:
ATTN_SetLowDisableIrq:
.ifdef INT0
.if COM_IRQ_BIT_ATTN == INT0
M_IO_READ r16, COM_IRQ_ADDR_ATTN ; disable irq for ATTN line
inr r16, COM_IRQ_ADDR_ATTN ; disable irq for ATTN line
cbr r16, (1<<COM_IRQ_BIT_ATTN)
M_IO_WRITE COM_IRQ_ADDR_ATTN, r16
outr COM_IRQ_ADDR_ATTN, r16
.endif
.endif
@@ -73,9 +76,9 @@ ATTN_SetHighEnableIrq:
.ifdef INT0
.if COM_IRQ_BIT_ATTN == INT0
M_IO_READ r16, COM_IRQ_ADDR_ATTN ; enable irq for ATTN line
inr r16, COM_IRQ_ADDR_ATTN ; enable irq for ATTN line
sbr r16, (1<<COM_IRQ_BIT_ATTN)
M_IO_WRITE COM_IRQ_ADDR_ATTN, r16
outr COM_IRQ_ADDR_ATTN, r16
.endif
.endif

47
avr/modules/uart_hw/uart.asm
View File

@@ -38,16 +38,17 @@ UART_Init:
ldi r17, 0
.endif
M_IO_WRITE UBRRH, r17
M_IO_WRITE UBRRL, r16
outr UBRRH, r17
outr UBRRL, r16
; set character format
.ifdef URSEL
ldi r16, (1<<URSEL) | (1<<USBS) | (1<<UCSZ1) | (1<<UCSZ0)
; ldi r16, (1<<URSEL) | (1<<USBS) | (1<<UCSZ1) | (1<<UCSZ0)
ldi r16, (1<<URSEL) | (1<<USBS) | (3<<UCSZ0)
.else
ldi r16, (1<<USBS) | (1<<UCSZ1) | (1<<UCSZ0)
.endif
M_IO_WRITE UCSRC, r16
outr UCSRC, r16
ret
; @end
@@ -69,16 +70,16 @@ UART_SendBytes:
; send bytes
UART_SendBytes_loop1:
M_IO_READ r16, UCSRA
inr r16, UCSRA
sbrs r16, UDRE
rjmp UART_SendBytes_loop1
ld r16, X+
M_IO_WRITE UDR, r16
outr UDR, r16
dec r17
brne UART_SendBytes_loop1
; wait until all data sent
UART_SendBytes_loop2:
M_IO_READ r16, UCSRA
inr r16, UCSRA
sbrs r16, TXC
rjmp UART_SendBytes_loop2
rcall UART_StopTx
@@ -100,7 +101,7 @@ UART_SendBytes_secRet:
UART_RecvPacket:
cpi r17, 3
brcs UART_RecvPacket_invalid
rcall uartRecvByteWithin10ms ; recv destination address
rcall uartRecvByteWithin10ms ; recv destination address (R16)
brcc UART_RecvPacket_ioError
cp r16, r18
breq UART_RecvPacket_forMe
@@ -158,10 +159,10 @@ uartRecvByteWithin10ms:
pop r22
pop r20
brcc uartRecvByteWithin10ms_end
M_IO_READ r16, UCSRA ; check for errors
inr r16, UCSRA ; check for errors
andi r16, (1<<FE) | (1<<DOR)
brne uartRecvByteWithin10ms_error
M_IO_READ r16, UDR ; read data byte
inr r16, UDR ; read data byte
sec
ret
uartRecvByteWithin10ms_error:
@@ -213,7 +214,7 @@ uartWaitForData10ms_gotit:
uartWaitForData1000Cycles:
ldi r20, 140 ; 1
uartWaitForData_loop:
M_IO_READ r22, UCSRA ; 2
inr r22, UCSRA ; 2
sbrc r22, RXC ; 2/3
rjmp uartWaitForData_gotit ; 2
dec r20 ; 1
@@ -235,14 +236,14 @@ uartWaitForData_gotit:
; @clobbers R16
UART_StartRx:
M_IO_READ r16, UCSRA ; clear errors
inr r16, UCSRA ; clear errors
cbr r16, (1<<FE) | (1<<DOR) | (1<<UPE)
sbr r16, (1<<RXC)
M_IO_WRITE UCSRA, r16
outr UCSRA, r16
M_IO_READ r16, UCSRB
inr r16, UCSRB
sbr r16, (1<<RXEN) ; enable receive
M_IO_WRITE UCSRB, r16
outr UCSRB, r16
ret
; @end
@@ -255,9 +256,9 @@ UART_StartRx:
; @clobbers R16
UART_StopRx:
M_IO_READ r16, UCSRB
inr r16, UCSRB
cbr r16, (1<<RXCIE | (1<<RXEN)) ; disable RX complete interrupt, disable receive
M_IO_WRITE UCSRB, r16
outr UCSRB, r16
ret
; @end
@@ -270,13 +271,13 @@ UART_StopRx:
; @clobbers R16
UART_StartTx:
M_IO_READ r16, UCSRA
inr r16, UCSRA
sbr r16, (1<<TXC) ; clear TXC interrupt
M_IO_WRITE UCSRA, r16
outr UCSRA, r16
M_IO_READ r16, UCSRB
inr r16, UCSRB
sbr r16, (1<<TXEN) ; enable transceive
M_IO_WRITE UCSRB, r16
outr UCSRB, r16
ret
; @end
@@ -290,9 +291,9 @@ UART_StartTx:
; @clobbers R16
UART_StopTx:
M_IO_READ r16, UCSRB
inr r16, UCSRB
cbr r16, (1<<UDRIE) | (1<<TXC) | (1<<TXEN) ; disable TX UDRE and TXC1 interrupt, enable transceive
M_IO_WRITE UCSRB, r16
outr UCSRB, r16
ret
; @end

4
avr/modules/xram/main.asm
View File

@@ -40,9 +40,9 @@ XRAM_Init:
sts xramLastAddress, r16
sts xramLastAddress+1, r16
M_IO_READ r16, MCUCR
inr r16, MCUCR
sbr r16, (1<<SRE)
M_IO_WRITE MCUCR, r16
outr MCUCR, r16
rcall xramWritePattern
rcall xramVerifyPattern