avr: added uart_bitbang module.
Started reorganizing COM module by splitting into higher and lower level functions.
This commit is contained in:
Martin Preuss
398
avr/modules/uart_bitbang/main.asm
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398
avr/modules/uart_bitbang/main.asm
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; ***************************************************************************
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; copyright : (C) 2024 by Martin Preuss
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; email : martin@libchipcard.de
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;
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; ***************************************************************************
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; * This file is part of the project "AqHome". *
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; * Please see toplevel file COPYING of that project for license details. *
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; ***************************************************************************
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; UART_BitBang_Init
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; UART_BitBang_Fini
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; UART_BitBang_Run
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; UART_BitBang_SendPacket:
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; UART_BitBang_GetNextReceivedPacket:
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; UART_BitBang_ReleaseReceivedPacket:
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.include "modules/com2/buffer.asm"
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.dseg
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uartBitbangDataBegin:
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uartBitbangRecvBuffersUsed: .byte 1
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uartBitbangMaxBuffersUsed: .byte 1
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uartBitbangRecvBuffersWritePos: .byte 1
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uartBitbangRecvBuffersReadPos: .byte 1
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uartBitbangRecvBuffers: .byte COM2_BUFFER_SIZE*UART_BITBANG_BUFFER_NUM
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uartBitbangDataEnd:
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.cseg
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; ---------------------------------------------------------------------------
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; @routine UART_BitBang_Init
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;
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; @return CFLAG set if okay, clear on error
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; @clobbers R16, R17, X, Y
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UART_BitBang_Init:
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; preset SRAM data area
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ldi xh, HIGH(uartBitbangDataBegin)
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ldi xl, LOW(uartBitbangDataBegin)
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clr r16
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ldi r17, (uartBitbangDataEnd-uartBitbangDataBegin)
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rcall Utils_FillSram
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; setup pins and interrupts
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cbi COM_TXD_DATA, COM_TXD_PIN ; disable internal pullup for TXD
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cbi COM_TXD_DDR, COM_TXD_PIN ; set TXD port as input
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cbi COM_RXD_DATA, COM_RXD_PIN ; disable internal pullup for RXD
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cbi COM_RXD_DDR, COM_RXD_PIN ; set RXD port as input
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cbi COM_ATTN_OUTPUT, COM_ATTN_PIN ; disable internal pullup for ATTN
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cbi COM_ATTN_DDR, COM_ATTN_PIN ; set ATTN port as input
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sbi COM_IRQ_ADDR_ATTN, COM_IRQ_BIT_ATTN ; enable pin change irq for ATTN line
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in r16, GIMSK ; enable pin change irq PCIE0 or PCIE1
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ori r16, (1<<COM_IRQ_GIMSK_ATTN)
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out GIMSK, R16
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ldi r16, (1<<COM_IRQ_GIFR_ATTN) ; clear pending irq by writing 1 to ATTN bit
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out GIFR, r16
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sec
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine UART_BitBang_Init
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;
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; @return CFLAG set if okay, clear on error
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; @clobbers R16, R17, X, Y
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UART_BitBang_Fini:
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cbi COM_TXD_DDR, COM_TXD_PIN ; set TXD port as input
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cbi COM_RXD_DDR, COM_RXD_PIN ; set RXD port as input
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cbi COM_ATTN_DDR, COM_ATTN_PIN ; set ATTN port as input
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cbi COM_IRQ_ADDR_ATTN, COM_IRQ_BIT_ATTN ; disable pin change irq for ATTN line
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in r16, GIMSK ; enable pin change irq PCIE0 or PCIE1
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andi r16, ~(1<<COM_IRQ_GIMSK_ATTN)
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out GIMSK, R16
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ldi r16, (1<<COM_IRQ_GIFR_ATTN) ; clear pending irq by writing 1 to ATTN bit
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out GIFR, r16
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine UART_BitBang_Run
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;
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; @clobbers any
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UART_BitBang_Run:
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine UART_BitBang_SendPacket
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; Send packet, if line free.
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;
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; @param X buffer to send
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; @return CFLAG: set if okay (packet sent), cleared on error
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; @clobbers r22, x (r18, r19, r22)
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UART_BitBang_SendPacket:
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rcall uartBitbang_SendPacket
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brcs UART_BitBang_SendPacket_okay
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cpi r16, COM2_ERROR_BUSY
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breq UART_BitBang_SendPacket_busyError
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cpi r16, COM2_ERROR_COLLISION
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breq UART_BitBang_SendPacket_collError
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; fall-through
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UART_BitBang_SendPacket_busyError:
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ldi xl, LOW(com2StatsBusyError)
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ldi xh, HIGH(com2StatsBusyError)
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rjmp UART_BitBang_SendPacket_incCounterRetNc
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UART_BitBang_SendPacket_collError:
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ldi xl, LOW(com2StatsCollisions)
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ldi xh, HIGH(com2StatsCollisions)
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UART_BitBang_SendPacket_incCounterRetNc:
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rcall Utils_IncrementCounter16 ; (r18, r19, r22)
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clc
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ret
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UART_BitBang_SendPacket_okay:
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ldi xl, LOW(com2StatsPacketsOut)
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ldi xh, HIGH(com2StatsPacketsOut)
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rcall Utils_IncrementCounter16 ; (r18, r19, r22)
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sec
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine UART_BitBang_GetNextReceivedPacket
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;
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; Get next received packet from receiption buffers.
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; Call @ref UART_BitBang_ReleaseReceivedPacket to release the packet buffer.
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;
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; @return CFLAG set if okay (packet received), cleared on error
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; @return X pointer to packet received
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; @clobbers r16, r17
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UART_BitBang_GetNextReceivedPacket:
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lds r16, uartBitbangRecvBuffersUsed
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tst r16
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breq UART_BitBang_GetNextReceivedPacket_retNc ; no buffers in use
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lds r16, uartBitbangRecvBuffersReadPos
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rcall uartBitbang_BufferPosToX ; get current read buffer to X (R16, R17)
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sec
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ret
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UART_BitBang_GetNextReceivedPacket_retNc:
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clc
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine UART_BitBang_ReleaseReceivedPacket
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;
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; Release first packet in queue from from receiption buffers (i.e. the one returned
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; by @ref UART_BitBang_GetNextReceivedPacket)
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;
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; @clobbers r16, r17, r21
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UART_BitBang_ReleaseReceivedPacket:
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rjmp COM2_BufferDeallocFront ; (r16, r17, r21)
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; ---------------------------------------------------------------------------
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; @routine uartBitbang_ReceivePacket
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;
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; Receive packet.
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;
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; @return CFLAG set if okay (packet received), cleared on error
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; @clobbers r16, r17, x (r18, r19, r20, r21, r22)
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uartBitbang_ReceivePacket:
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rcall uartBitbang_BufferAlloc ; (r16, r17, r21)
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brcs uartBitbang_ReceivePacket_bufferAvailable
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ldi xl, LOW(com2StatsNoBufferError) ; buffer in use, don't release
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ldi xh, HIGH(com2StatsNoBufferError) ; just increment error counter
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rcall Utils_IncrementCounter16 ; (r18, r19, 22)
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clc
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ret
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uartBitbang_ReceivePacket_bufferAvailable:
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push xl
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push xh
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lds r16, com2Address
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ldi r17, (COM2_BUFFER_SIZE-3) ; buffer size minus dst addr, payload len, crc byte
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rcall uartBitbang_ReceivePacketIntoBuffer ; r16, r17, r18, X (r19, r20, r21, r22)
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pop xh
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pop xl
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brcc uartBitbang_ReceivePacket_error
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rcall com2CheckMessageInBuffer ; (R16, R17, R18, R19, R20, X)
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brcc uartBitbang_ReceivePacket_dataError
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; everything okay
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ldi xl, LOW(com2StatsPacketsIn)
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ldi xh, HIGH(com2StatsPacketsIn)
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rcall Utils_IncrementCounter16 ; (r18, r19, 22)
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sec
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ret
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uartBitbang_ReceivePacket_error:
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cpi r16, COM2_ERROR_NOTFORME
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breq uartBitbang_ReceivePacket_notForMe
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cpi r16, COM2_ERROR_DATAERROR
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breq uartBitbang_ReceivePacket_dataError
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;cpi r16, COM2_ERROR_IOERROR
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;breq uartBitbang_ReceivePacket_ioError
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;rjmp uartBitbang_ReceivePacket_retnc
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rjmp uartBitbang_ReceivePacket_ioError ; default to IO ERROR
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uartBitbang_ReceivePacket_ioError:
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ldi xl, LOW(com2StatsIoError)
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ldi xh, HIGH(com2StatsIoError)
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rjmp uartBitbang_ReceivePacket_incCounterDeallocNc
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uartBitbang_ReceivePacket_dataError:
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ldi xl, LOW(com2StatsContentError)
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ldi xh, HIGH(com2StatsContentError)
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rjmp uartBitbang_ReceivePacket_incCounterDeallocNc
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uartBitbang_ReceivePacket_notForMe:
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ldi xl, LOW(com2StatsNotForMe)
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ldi xh, HIGH(com2StatsNotForMe)
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rjmp uartBitbang_ReceivePacket_incCounterDeallocNc
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uartBitbang_ReceivePacket_incCounterDeallocNc:
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rcall Utils_IncrementCounter16 ; (r18, r19, 22)
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uartBitbang_ReceivePacket_deallocRetnc:
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rcall uartBitbang_BufferDeallocBack
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uartBitbang_ReceivePacket_retnc:
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clc
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ret
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; @end
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; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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; Buffer Management
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; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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; ---------------------------------------------------------------------------
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; @routine uartBitbang_BufferAlloc
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;
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; Allocate a transfer buffer.
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;
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; @return CFLAG set if okay, clear otherwise
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; @return X pointer to allocated buffer in SRAM
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; @clobbers r16, r17, r21
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uartBitbang_BufferAlloc:
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COM2_M_BufferAlloc UART_BITBANG_BUFFER_NUM, uartBitbangMaxBuffersUsed, uartBitbangRecvBuffersUsed, uartBitbangRecvBuffersWritePos
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine uartBitbang_BufferDeallocBack
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;
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; Release a transfer buffer at the end of the list by decreasing the write pos.
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; This releases the last allocated buffer!
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;
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; @return CFLAG set if okay, clear otherwise
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; @clobbers r16, r17, r21
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uartBitbang_BufferDeallocBack:
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COM2_M_BufferDeallocBack UART_BITBANG_BUFFER_NUM, uartBitbangRecvBuffersUsed, uartBitbangRecvBuffersWritePos
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine uartBitbang_BufferDeallocFront
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;
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; Release a transfer buffer by increasing the read pos.
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;
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; @return CFLAG set if okay, clear otherwise
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; @clobbers r16, r17, r21
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uartBitbang_BufferDeallocFront:
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COM2_M_BufferDeallocFront UART_BITBANG_BUFFER_NUM, uartBitbangRecvBuffersUsed, uartBitbangRecvBuffersReadPos
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine uartBitbang_BufferPosToX
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;
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; Get a pointer to the SRAM position of the given buffer.
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; CAVE: Code must correspond to COM2_BUFFER_SIZE!!
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;
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; @param R16 buffer number (starting with 0)
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; @return X pointer to buffer in SRAM
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; @clobbers R16, R17
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uartBitbang_BufferPosToX:
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COM2_M_BufferPosToX uartBitbangRecvBuffers
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ret
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; @end
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; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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; ISR
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; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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uartBitbangIsrPcint0:
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push r15
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in r15, SREG
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sbic COM_ATTN_INPUT, COM_ATTN_PIN
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rjmp uartBitbangIsrPcint0_end
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; low, read packet
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push r1
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push r16
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push r17
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push r18
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push r19
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push r20
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push r21
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push r22
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push xh
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push xl
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push r15
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rcall uartBitbang_ReceivePacket ; (r16, r17, r18, r19, r20, r21, r22, x)
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pop r15
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lds xl, com2Interrupts
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lds xh, com2Interrupts+1
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adiw xh:xl, 1
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sts com2Interrupts, xl
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sts com2Interrupts+1, xh
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pop xl
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pop xh
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pop r22
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pop r21
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pop r20
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pop r19
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pop r18
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pop r17
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pop r16
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pop r1
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uartBitbangIsrPcint0_end:
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out SREG, r15
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pop r15
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reti
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; set routine functions
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.equ COMIO_Init = UART_BitBang_Init
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.equ COMIO_Fini = UART_BitBang_Fini
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.equ COMIO_Run = UART_BitBang_Run
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.equ COMIO_SendPacket = UART_BitBang_SendPacket
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.equ COMIO_GetNextReceivedPacket = UART_BitBang_GetNextReceivedPacket
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.equ COMIO_ReleaseReceivedPacket = UART_BitBang_ReleaseReceivedPacket
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