avr: added uart_bitbang module.
Started reorganizing COM module by splitting into higher and lower level functions.
This commit is contained in:
Martin Preuss
186
avr/modules/uart_bitbang/bytelevel.asm
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186
avr/modules/uart_bitbang/bytelevel.asm
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; ***************************************************************************
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; copyright : (C) 2024 by Martin Preuss
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; email : martin@libchipcard.de
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;
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; ***************************************************************************
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; * This file is part of the project "AqHome". *
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; * Please see toplevel file COPYING of that project for license details. *
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; ***************************************************************************
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; ---------------------------------------------------------------------------
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; @macro UART_BB_M_WAIT_FOR_PIN_LOW IN_REG_DATA, IN_PINNUM
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; 0 1
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; Wait for a pin to become low
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; @param %0 DATA register for input pin (e.g. PINB)
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; @param %1 pin number for input (e.g. PORTB1)
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; @return CFLAG set if okay, clear otherwise
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; @clobbers R17, R22
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.macro UART_BB_M_WAIT_FOR_PIN_LOW
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ldi r17, 200
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l_loop:
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sbis @0, @1
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rjmp l_reached
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Utils_WaitNanoSecs 5000, 0, r22 ; wait for 5us
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dec r17
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brne l_loop
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clc
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rjmp l_end
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l_reached:
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sec
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l_end:
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.endmacro
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; @end
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; ---------------------------------------------------------------------------
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; @macro UART_BB_M_WAIT_FOR_PIN_HIGH IN_REG_DATA, IN_PINNUM
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; 0 1
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; Wait for a pin to become high
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; @param %0 DATA register for input pin (e.g. PINB)
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; @param %1 pin number for input (e.g. PORTB1)
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; @return CFLAG set if okay, clear otherwise
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; @clobbers R17, R22
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.macro UART_BB_M_WAIT_FOR_PIN_HIGH
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ldi r17, 200
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l_loop:
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sbic @0, @1
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rjmp l_reached
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Utils_WaitNanoSecs 5000, 0, r22 ; wait for 5us
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dec r17
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brne l_loop
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clc
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rjmp l_end
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l_reached:
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sec
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l_end:
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.endmacro
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; @end
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; ---------------------------------------------------------------------------
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; @routine uartBitbang_SendByte
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;
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; Send a byte.
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; We only set the data pin to low at the beginning for the startbit. After that
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; we only change the pin direction (e.g. input vs output):
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; - for 0 bit: set DDR to output, forcing the data line low
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; - for 1 bit: set DDR to input, letting the external pullup R pull the data line to HIGH
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; since the output pin is still set to 0 the internal pullup is disabled
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; Expects interrupts to be disabled.
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;
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; @param R16 byte to send
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; @return CFLAG set if okay, clear otherwise
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; @clobbers R16, R21, R22
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uartBitbang_SendByte:
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ldi r21, 8 ; +1 bits left
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; send startbit
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cbi COM_TXD_DATA, COM_TXD_PIN ; +2 set DATA low
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sbi COM_TXD_DDR, COM_TXD_PIN ; +2 set DATA as output
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Utils_WaitNanoSecs COM_BIT_LENGTH, 1, r22 ; wait for one bit duration
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; send data bits
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uartBitbang_SendByte_loop: ; 9 for low bit
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lsr r16 ; 1+ bit to send -> CARRY
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brcs uartBitbang_SendByte_setHigh ; HI: +2, LO: +1
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uartBitbang_SendByte_setLow:
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sbi COM_TXD_DDR, COM_TXD_PIN ; +2 set DATA as output
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Utils_WaitNanoSecs COM_BIT_LENGTH, 9, r22
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rjmp uartBitbang_SendByte_loopEnd ; +2
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uartBitbang_SendByte_setHigh:
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cbi COM_TXD_DDR, COM_TXD_PIN ; +2 set DATA as input, pullup R makes it ONE
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nop ; +1 (to make pin change available)
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Utils_WaitNanoSecs COM_HALFBIT_LENGTH, 0, r22 ; wait for half a bit length for line to safely settle
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sbis COM_RXD_DATA, COM_RXD_PIN ; +1 if no skip, +2 if skipped
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rjmp uartBitbang_SendByte_error ; +2 if error (collision: we wanted line to be high but it is low)
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Utils_WaitNanoSecs COM_HALFBIT_LENGTH, 11, r22
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uartBitbang_SendByte_loopEnd:
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dec r21 ; +1
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brne uartBitbang_SendByte_loop ; +2, sum per loop: 10 cycles
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; send stopbit
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cbi COM_TXD_DDR, COM_TXD_PIN ; +2 set DATA as input, pullup R makes it ONE
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Utils_WaitNanoSecs COM_BIT_LENGTH, 0, r22 ; wait for one bit length
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sec
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ret
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uartBitbang_SendByte_error:
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clc
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine uartBitbangReceiveByte
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;
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; Read a byte.
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; Expects interrupts to be disabled.
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;
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; @return CFLAG set if okay, clear otherwise
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; @return R16 byte received
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; @clobbers R16, R20, R21, R22 (R17)
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uartBitbang_ReceiveByte:
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ldi r21, 8 ; bits left
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clr r20 ; byte currently receiving
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; wait for startbit
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rcall uartBitbang_WaitForDataLow ; (R17, R22)
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brcc uartBitbang_ReceiveByte_error
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Utils_WaitNanoSecs COM_HALFBIT_LENGTH, 10, r22 ; goto middle of startbit to maximize sync stability
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uartBitbang_ReceiveByte_loop:
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Utils_WaitNanoSecs COM_BIT_LENGTH, 8, r22 ; 8 cycles used in the complete loop between waits
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sec ; +1
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sbic COM_RXD_DATA, COM_RXD_PIN ; LOW: +2, HIGH: +1
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rjmp uartBitbang_ReceiveByte_shiftIn ; HIGH: +2, rjmp, use set CFLAG
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clc ; LOW: +1
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uartBitbang_ReceiveByte_shiftIn:
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ror r20 ; +1
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dec r21 ; +1
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brne uartBitbang_ReceiveByte_loop ; +2, sum per loop: 8 cycles
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rcall uartBitbang_WaitForDataHigh ; wait for start of stopbit
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brcc uartBitbang_ReceiveByte_error
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mov r16, r20
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sec
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ret
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uartBitbang_ReceiveByte_error:
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clc
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine uartBitbang_WaitForDataLow
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;
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; Wait for data pin to become low
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; @return CFLAG set if okay, clear otherwise
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; @clobbers R17, R22
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uartBitbang_WaitForDataLow:
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UART_BB_M_WAIT_FOR_PIN_LOW COM_RXD_DATA, COM_RXD_PIN
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine uartBitbang_WaitForDataHigh
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;
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; Wait for data pin to become high
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; @return CFLAG set if okay, clear otherwise
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; @clobbers R17, R22
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uartBitbang_WaitForDataHigh:
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UART_BB_M_WAIT_FOR_PIN_LOW COM_RXD_DATA, COM_RXD_PIN
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ret
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; @end
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