r05, comOnUart0 and comOnUart1 work!

This commit is contained in:
Martin Preuss
2025-07-06 17:19:59 +02:00
parent 439e787d37
commit 81b008af0c
5 changed files with 302 additions and 566 deletions

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@@ -129,12 +129,12 @@
reti ; 21: SPI SPI Serial Transfer Complete reti ; 21: SPI SPI Serial Transfer Complete
reti ; 22: USART0_RXS USART0 Rx Start reti ; 22: USART0_RXS USART0 Rx Start
rjmp ComOnUart0_RxCharIsr ; 23: USART0_RXC USART0 Rx Complete rjmp ComOnUart0_RxCharIsr ; 23: USART0_RXC USART0 Rx Complete
rjmp ComOnUart0_TxUdreIsr ; 24: USART0_DRE USART0 Data Register Empty reti ; 24: USART0_DRE USART0 Data Register Empty
rjmp ComOnUart0_TxCharIsr ; 25: USART0_TXC USART0 Tx Complete reti ; 25: USART0_TXC USART0 Tx Complete
reti ; 26: USART1_RXS USART1 Rx Start reti ; 26: USART1_RXS USART1 Rx Start
rjmp ComOnUart1_RxCharIsr ; 27: USART1_RXC USART1 Rx Complete rjmp ComOnUart1_RxCharIsr ; 27: USART1_RXC USART1 Rx Complete
rjmp ComOnUart1_TxUdreIsr ; 28: USART1_DRE USART1 Data Register Empty reti ; 28: USART1_DRE USART1 Data Register Empty
rjmp ComOnUart1_TxCharIsr ; 29: USART1_TXC USART1 Tx Complete reti ; 29: USART1_TXC USART1 Tx Complete
reti ; 30: TWI Two-Wire-Interface reti ; 30: TWI Two-Wire-Interface
reti ; 31: RESERVED reserved reti ; 31: RESERVED reserved
@@ -162,6 +162,13 @@ firmwareStart:
; @routine onSystemStart ; @routine onSystemStart
onSystemStart: onSystemStart:
; set interface number for UART0
ldi r16, COMONUART0_IFACENUM
sts comOnUart0_iface+NET_IFACE_OFFS_IFACENUM, r16
; set interface number for UART1
ldi r16, COMONUART1_IFACENUM
sts comOnUart1_iface+NET_IFACE_OFFS_IFACENUM, r16
ret ret
; @end ; @end
@@ -230,7 +237,7 @@ checkRecvdMsg:
; forward to other interface ; forward to other interface
ld r17, X ld r17, X
andi r17, (NET_IFACE_BUFFER_IFACENUM1_BIT | NET_IFACE_BUFFER_IFACENUM0_BIT) andi r17, (1<<NET_IFACE_BUFFER_IFACENUM1_BIT) | (1<<NET_IFACE_BUFFER_IFACENUM0_BIT)
rcall reverseInterfaceNum ; (R16, R17) rcall reverseInterfaceNum ; (R16, R17)
; ldi r17, COMONUART0_IFACENUM ; DEBUG: send everything to uart0 to test that code first ; ldi r17, COMONUART0_IFACENUM ; DEBUG: send everything to uart0 to test that code first
rcall addMsgToInterface rcall addMsgToInterface
@@ -288,6 +295,7 @@ letSysHandleMsg_end:
reverseInterfaceNum: reverseInterfaceNum:
ldi r16, (1<<NET_IFACE_BUFFER_IFACENUM1_BIT) | (1<<NET_IFACE_BUFFER_IFACENUM0_BIT) ldi r16, (1<<NET_IFACE_BUFFER_IFACENUM1_BIT) | (1<<NET_IFACE_BUFFER_IFACENUM0_BIT)
eor r17, r16 eor r17, r16
and r17, r16
ret ret
; @end ; @end
@@ -319,6 +327,9 @@ addMsgToInterface_end:
sendPacketsIface2In: sendPacketsIface2In:
ldi yl, LOW(netInterfaceData) ldi yl, LOW(netInterfaceData)
ldi yh, HIGH(netInterfaceData) ldi yh, HIGH(netInterfaceData)
; ldi yl, LOW(comOnUart1_iface)
; ldi yh, HIGH(comOnUart1_iface)
ldi r17, AQHOME_VALUEID_STATS_PACKETS_IN2 ldi r17, AQHOME_VALUEID_STATS_PACKETS_IN2
lds r18, comOnUart1_iface+NET_IFACE_OFFS_PACKETSIN_LOW lds r18, comOnUart1_iface+NET_IFACE_OFFS_PACKETSIN_LOW
lds r19, comOnUart1_iface+NET_IFACE_OFFS_PACKETSIN_HIGH lds r19, comOnUart1_iface+NET_IFACE_OFFS_PACKETSIN_HIGH

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@@ -75,8 +75,8 @@
;#define MODULES_MOTION ;#define MODULES_MOTION
#define MODULES_NETWORK #define MODULES_NETWORK
;#define MODULES_TTYONUART1 ;#define MODULES_TTYONUART1
;#define MODULES_COMONUART0 #define MODULES_COMONUART0
#define MODULES_COMONUART1 ;#define MODULES_COMONUART1
#define APPS_STATS #define APPS_STATS
#define APPS_NETWORK #define APPS_NETWORK
@@ -113,9 +113,10 @@
rjmp BOOTLOADER_ADDR ; 1: RESET Reset vector use this for flashed system rjmp BOOTLOADER_ADDR ; 1: RESET Reset vector use this for flashed system
reti ; 2: INT0 External Interrupt Request 0 reti ; 2: INT0 External Interrupt Request 0
; rjmp ComOnUart0_AttnChangeIsr ; 3: PCINT0 Pin Change Interrupt 0 rjmp ComOnUart0_AttnChangeIsr ; 3: PCINT0 Pin Change Interrupt 0
reti ; 3: PCINT0 Pin Change Interrupt 0 ; reti ; 3: PCINT0 Pin Change Interrupt 0
rjmp ComOnUart1_AttnChangeIsr ; 4: PCINT1 Pin Change Interrupt 1 ; rjmp ComOnUart1_AttnChangeIsr ; 4: PCINT1 Pin Change Interrupt 1
reti ; 4: PCINT1 Pin Change Interrupt 1
reti ; 5: WDT Watchdog Time-out reti ; 5: WDT Watchdog Time-out
reti ; 6: TIM1_CAPT Timer/Counter1 Capture Event reti ; 6: TIM1_CAPT Timer/Counter1 Capture Event
reti ; 7: TIM1_COMPA (OC1A) Timer/Counter1 Compare Match A reti ; 7: TIM1_COMPA (OC1A) Timer/Counter1 Compare Match A
@@ -134,19 +135,17 @@
reti ; 20: TIM2_OVF (OVF2) Timer/Counter2 Overflow reti ; 20: TIM2_OVF (OVF2) Timer/Counter2 Overflow
reti ; 21: SPI SPI Serial Transfer Complete reti ; 21: SPI SPI Serial Transfer Complete
reti ; 22: USART0_RXS USART0 Rx Start reti ; 22: USART0_RXS USART0 Rx Start
; rjmp ComOnUart0_RxCharIsr ; 23: USART0_RXC USART0 Rx Complete rjmp ComOnUart0_RxCharIsr ; 23: USART0_RXC USART0 Rx Complete
reti ; 23: USART0_RXC USART0 Rx Complete ; reti ; 23: USART0_RXC USART0 Rx Complete
; rjmp ComOnUart0_TxUdreIsr ; 24: USART0_DRE USART0 Data Register Empty ; rjmp ComOnUart0_TxUdreIsr ; 24: USART0_DRE USART0 Data Register Empty
reti ; 24: USART0_DRE USART0 Data Register Empty reti ; 24: USART0_DRE USART0 Data Register Empty
; rjmp ComOnUart0_TxCharIsr ; 25: USART0_TXC USART0 Tx Complete ; rjmp ComOnUart0_TxCharIsr ; 25: USART0_TXC USART0 Tx Complete
reti ; 25: USART0_TXC USART0 Tx Complete reti ; 25: USART0_TXC USART0 Tx Complete
reti ; 26: USART1_RXS USART1 Rx Start reti ; 26: USART1_RXS USART1 Rx Start
rjmp ComOnUart1_RxCharIsr ; 27: USART1_RXC USART1 Rx Complete ; rjmp ComOnUart1_RxCharIsr ; 27: USART1_RXC USART1 Rx Complete
; reti ; 27: USART1_RXC USART1 Rx Complete reti ; 27: USART1_RXC USART1 Rx Complete
rjmp ComOnUart1_TxUdreIsr ; 28: USART1_DRE USART1 Data Register Empty reti ; 28: USART1_DRE USART1 Data Register Empty
; reti ; 28: USART1_DRE USART1 Data Register Empty reti ; 29: USART1_TXC USART1 Tx Complete
rjmp ComOnUart1_TxCharIsr ; 29: USART1_TXC USART1 Tx Complete
; reti ; 29: USART1_TXC USART1 Tx Complete
reti ; 30: TWI Two-Wire-Interface reti ; 30: TWI Two-Wire-Interface
reti ; 31: RESERVED reserved reti ; 31: RESERVED reserved
@@ -175,11 +174,11 @@ firmwareStart:
onSystemStart: onSystemStart:
; set interface number for UART0 ; set interface number for UART0
; ldi r16, COMONUART0_IFACENUM ldi r16, COMONUART0_IFACENUM
; sts comOnUart0_iface+NET_IFACE_OFFS_IFACENUM, r16 sts comOnUart0_iface+NET_IFACE_OFFS_IFACENUM, r16
; set interface number for UART1 ; set interface number for UART1
ldi r16, COMONUART1_IFACENUM ; ldi r16, COMONUART1_IFACENUM
sts comOnUart1_iface+NET_IFACE_OFFS_IFACENUM, r16 ; sts comOnUart1_iface+NET_IFACE_OFFS_IFACENUM, r16
ret ret
; @end ; @end
@@ -236,7 +235,7 @@ onMessageReceived:
; --------------------------------------------------------------------------- ; ---------------------------------------------------------------------------
; defines for network interface ; defines for network interface
.equ netInterfaceData = comOnUart1_iface .equ netInterfaceData = comOnUart0_iface
;.equ netInterfaceData2 = comOnUart1_iface ;.equ netInterfaceData2 = comOnUart1_iface

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@@ -33,15 +33,16 @@ ComOnUart0_Init:
ldi yl, LOW(comOnUart0_iface) ldi yl, LOW(comOnUart0_iface)
ldi yh, HIGH(comOnUart0_iface) ldi yh, HIGH(comOnUart0_iface)
rcall NET_Interface_Init ; (R16, R17, X) rcall NET_Interface_Init ; (R16, R17, X)
ldi r16, 0xff
std Y+UART_HW2_IFACE_OFFS_WRITEBUFNUM, r16
ldi r16, UART_HW2_MODE_IDLE ldi r16, UART_HW2_MODE_IDLE
std Y+UART_HW2_IFACE_OFFS_MODE, r16 std Y+UART_HW2_IFACE_OFFS_MODE, r16
clr r16 clr r16
std Y+NET_IFACE_OFFS_IFACENUM, r16 std Y+NET_IFACE_OFFS_IFACENUM, r16
rcall comOnUart0SetAttnInput rcall comOnUart0SetAttnInput
sbi COM_IRQ_ADDR_ATTN0, COM_IRQ_BIT_ATTN0 ; enable pin change irq for ATTN line inr r16, COM_IRQ_ADDR_ATTN0
sbr r16, (1<<COM_IRQ_BIT_ATTN0) ; enable pin change irq for ATTN line
outr COM_IRQ_ADDR_ATTN0, r16
inr r16, GIMSK ; enable pin change irq PCIE0 or PCIE1 inr r16, GIMSK ; enable pin change irq PCIE0 or PCIE1
sbr r16, (1<<COM_IRQ_GIMSK_ATTN0) sbr r16, (1<<COM_IRQ_GIMSK_ATTN0)
outr GIMSK, r16 outr GIMSK, r16
@@ -143,70 +144,6 @@ comOnUart0StartReading:
; ---------------------------------------------------------------------------
; @routine comOnUart0StartWriting
;
; @param Y pointer to interface data in SRAM
; @param R16 buffer number
; @return CFLAG set if writing started, cleared otherwise
; @clobbers R16, R17, X, Z (R22, R24, R25)
comOnUart0StartWriting:
push r15
inr r15, SREG
cli
rcall comOnUart0StartWriting_noIrq
brcc comOnUart0StartWriting_clc
outr SREG, r15
pop r15
sec
ret
comOnUart0StartWriting_clc:
outr SREG, r15
pop r15
clc
ret
comOnUart0StartWriting_noIrq:
rcall comOnUart0AcquireAttn ; (R22)
brcc comOnUart0StartWriting_ebusy
; copy buffer
rcall NET_Buffer_Locate ; (R17)
std Y+UART_HW2_IFACE_OFFS_WRITEBUFNUM, r16
adiw xh:xl, NETMSG_OFFS_MSGLEN+1
ld r17, X
sbiw xh:xl, NETMSG_OFFS_MSGLEN+1
subi r17, -3 ; add dest addr, msglen, crc
; TODO: check size!
std Y+UART_HW2_IFACE_OFFS_BUFUSED, r17
std Y+UART_HW2_IFACE_OFFS_BUFLEFT, r17
; copy into IFACE buffer
mov zl, yl
mov zh, yh
adiw zh:zl, UART_HW2_IFACE_OFFS_BUFFER ; dest
std Y+UART_HW2_IFACE_OFFS_BUFPOS_LOW, zl
std Y+UART_HW2_IFACE_OFFS_BUFPOS_HIGH, zh
adiw xh:xl, 1 ; src (skip buffer header)
comOnUart0StartWriting_loop:
ld r16, X+
st Z+, r16
dec r17
brne comOnUart0StartWriting_loop
ldi r16, UART_HW2_MODE_WRITING
rcall comOnUart0SetMode ; (R17)
rcall comOnUart0StartTx ; should be the last call here (R16)
sec
rjmp comOnUart0StartWriting_end
comOnUart0StartWriting_ebusy:
ldi r16, NET_IFACE_OFFS_ERR_BUSY_LOW
rcall NET_Interface_IncCounter16 ; (R24, R25)
clc
comOnUart0StartWriting_end:
ret
; @end
; --------------------------------------------------------------------------- ; ---------------------------------------------------------------------------
; @routine ComOnUart0_Run @global ; @routine ComOnUart0_Run @global
; ;
@@ -251,10 +188,7 @@ comOnUart0ModeJumpTable:
rjmp comOnUart0RunIdle rjmp comOnUart0RunIdle
rjmp comOnUart0RunReading rjmp comOnUart0RunReading
rjmp comOnUart0RunSkipping rjmp comOnUart0RunSkipping
rjmp comOnUart0RunMsgReceived
rjmp comOnUart0RunWriting rjmp comOnUart0RunWriting
rjmp comOnUart0RunWaitBufferEmpty
rjmp comOnUart0RunMsgSent
; @end ; @end
@@ -263,15 +197,48 @@ comOnUart0ModeJumpTable:
; @routine comOnUart0RunIdle ; @routine comOnUart0RunIdle
; ;
; @param Y pointer to interface data in SRAM ; @param Y pointer to interface data in SRAM
; @clobbers R16, R17, R24, R25, X, Z ; @clobbers R16, R17, R22, R24, R25, X
comOnUart0RunIdle: comOnUart0RunIdle:
; look for outbound message push r15
rcall NET_Interface_PeekNextOutgoingMsgNum ; r16=msgNum inr r15, SREG
brcc comOnUart0RunIdle_end ; no outmsg in queue cli
rcall comOnUart0StartWriting ; (R16, R17, R22, R24, R25, X, Z) ; look for outbound message
rcall NET_Interface_PeekNextOutgoingMsgNum ; r16=msgNum
brcs comOnUart0RunIdle_haveMsg
out SREG, r15
pop r15
rjmp comOnUart0RunIdle_end
comOnUart0RunIdle_haveMsg:
mov r24, r16
ldi r16, UART_HW2_MODE_WRITING
rcall comOnUart0SetMode ; (R17)
mov r16, r24
out SREG, r15
pop r15
push r16
rcall NET_Buffer_Locate ; (R17)
adiw xh:xl, 1
rcall comOnUart0SendMsg ; (R16, R17, R22, R24, R25, X)
push r15
inr r15, SREG ; save SREG (no CLI, we want to save CFLAG only)
ldi r16, UART_HW2_MODE_IDLE
rcall comOnUart0SetMode ; (R17)
out SREG, r15 ; restore SREG
pop r15
pop r16
brcc comOnUart0RunIdle_end brcc comOnUart0RunIdle_end
rcall NET_Interface_GetNextOutgoingMsgNum ; take current msg off the queue
push r15
inr r15, SREG
cli
rcall NET_Interface_GetNextOutgoingMsgNum ; take current msg off the queue
rcall NET_Buffer_ReleaseByNum ; (R16, X)
out SREG, r15
pop r15
sec
comOnUart0RunIdle_end: comOnUart0RunIdle_end:
ret ret
; @end ; @end
@@ -308,12 +275,12 @@ comOnUart0RunSkipping_end:
; --------------------------------------------------------------------------- ; ---------------------------------------------------------------------------
; @routine comOnUart0RunMsgReceived ; @routine comOnUart0HandleMsgReceived
; ;
; @param Y pointer to interface data in SRAM ; @param Y pointer to interface data in SRAM
; @clobbers R16, R17, R18, X, Z (R19, R20, R24, R25) ; @clobbers R16, R17, R18, X, Z (R19, R20, R24, R25)
comOnUart0RunMsgReceived: comOnUart0HandleMsgReceived:
mov xl, yl mov xl, yl
mov xh, yh mov xh, yh
adiw xh:xl, UART_HW2_IFACE_OFFS_BUFFER adiw xh:xl, UART_HW2_IFACE_OFFS_BUFFER
@@ -371,42 +338,6 @@ comOnUart0RunWriting:
; ---------------------------------------------------------------------------
; @routine comOnUart0RunWaitBufferEmpty
;
; @clobbers none
comOnUart0RunWaitBufferEmpty:
; TODO: check for timeout etc.
ret
; @end
; ---------------------------------------------------------------------------
; @routine comOnUart0RunWriting
;
; @param Y pointer to interface data in SRAM
; @clobbers R16 (R17, R22, R24, R25, X)
comOnUart0RunMsgSent:
ldd r16, Y+UART_HW2_IFACE_OFFS_WRITEBUFNUM
rcall NET_Buffer_ReleaseByNum ; (R16, X)
ldi r16, 0xff
std Y+UART_HW2_IFACE_OFFS_WRITEBUFNUM, r16
ldi r16, NET_IFACE_OFFS_PACKETSOUT_LOW
rcall NET_Interface_IncCounter16 ; (R24, R25)
ldi r16, UART_HW2_MODE_IDLE
rcall comOnUart0SetMode ; (R17)
rcall comOnUart0SetAttnInput ; release ATTN (none)
rcall Utils_WaitFor10MicroSecs ; make sure ATTN is at least high for a short period (R22)
ret
; @end
; --------------------------------------------------------------------------- ; ---------------------------------------------------------------------------
; @routine comOnUart0AcquireAttn ; @routine comOnUart0AcquireAttn
; ;
@@ -467,10 +398,11 @@ comOnUart0StopRx:
comOnUart0StartTx: comOnUart0StartTx:
inr r16, UCSR0A inr r16, UCSR0A
cbr r16, (1<<TXC0) ; clear TXCn interrupt cbr r16, (1<<TXC0) ; clear TXCn interrupt
outr UCSR0A, r16 outr UCSR0A, r16
inr r16, UCSR0B inr r16, UCSR0B
sbr r16, (1<<UDRIE0) | (1<<TXCIE0) | (1<<TXEN0) ; enable TX UDRE and TXC0 interrupt, enable transceive cbr r16, (1<<UDRIE0) | (1<<TXCIE0) ; disable TX UDRE and TXC0 interrupt, enable transceive
sbr r16, (1<<TXEN0) ; enable TX UDRE and TXC0 interrupt, enable transceive
outr UCSR0B, r16 outr UCSR0B, r16
ret ret
; @end ; @end
@@ -484,7 +416,7 @@ comOnUart0StartTx:
comOnUart0StopTx: comOnUart0StopTx:
inr r16, UCSR0B inr r16, UCSR0B
cbr r16, (1<<UDRIE0) | (1<<TXCIE0) | (1<<TXEN0) ; disable TX UDRE and TXC0 interrupt, enable transceive cbr r16, (1<<UDRIE0) | (1<<TXCIE0) | (1<<TXEN0) ; disable TX UDRE and TXC0 interrupt, disable transceive
outr UCSR0B, r16 outr UCSR0B, r16
ret ret
; @end ; @end
@@ -506,6 +438,13 @@ comOnUart0SetAttnInput:
.else .else
cbi COM_ATTN0_OUTPUT, COM_ATTN0_PIN ; disable pullup on ATTN cbi COM_ATTN0_OUTPUT, COM_ATTN0_PIN ; disable pullup on ATTN
.endif .endif
push r16
inr r16, COM_IRQ_ADDR_ATTN0
sbr r16, (1<<COM_IRQ_BIT_ATTN0) ; enable pin change irq for ATTN line
outr COM_IRQ_ADDR_ATTN0, r16
pop r16
ret ret
; @end ; @end
@@ -519,8 +458,13 @@ comOnUart0SetAttnInput:
; @clobbers none ; @clobbers none
comOnUart0SetAttnLow: comOnUart0SetAttnLow:
sbi COM_ATTN0_DDR, COM_ATTN0_PIN ; set ATTN as output push r16
cbi COM_ATTN0_OUTPUT, COM_ATTN0_PIN ; set ATTN low inr r16, COM_IRQ_ADDR_ATTN0
cbr r16, (1<<COM_IRQ_BIT_ATTN0) ; disable pin change irq for ATTN line
outr COM_IRQ_ADDR_ATTN0, r16
pop r16
sbi COM_ATTN0_DDR, COM_ATTN0_PIN ; set ATTN as output
cbi COM_ATTN0_OUTPUT, COM_ATTN0_PIN ; set ATTN low
ret ret
; @end ; @end
@@ -552,21 +496,29 @@ ComOnUart0_RxCharIsr:
push r16 push r16
push r17 push r17
push r18 push r18
push r24 push r19
push r25 push r20
push xl push r24
push xh push r25
push yl push xl
push yh push xh
ldi yl, LOW(comOnUart0_iface) push yl
ldi yh, HIGH(comOnUart0_iface) push yh
rcall comOnUart0RxCharIsr ; (R16, R17, R18, R24, R25, X) push zl
pop yh push zh
pop yl ldi yl, LOW(comOnUart0_iface)
pop xh ldi yh, HIGH(comOnUart0_iface)
pop xl rcall comOnUart0RxCharIsr ; (R16, R17, R18, R19, R20, R24, R25, X, Z)
pop r25 pop zh
pop r24 pop zl
pop yh
pop yl
pop xh
pop xl
pop r25
pop r24
pop r20
pop r19
pop r18 pop r18
pop r17 pop r17
pop r16 pop r16
@@ -577,62 +529,6 @@ ComOnUart0_RxCharIsr:
; ---------------------------------------------------------------------------
; @routine ComOnUart0_TxUdreIsr @global @isr
;
; @clobbers none
ComOnUart0_TxUdreIsr:
push r15
in r15, SREG
push r16
push r17
push xl
push xh
push yl
push yh
ldi yl, LOW(comOnUart0_iface)
ldi yh, HIGH(comOnUart0_iface)
rcall comOnUart0TxUdreIsr ; (R16, R17, X)
pop yh
pop yl
pop xh
pop xl
pop r17
pop r16
out SREG, r15
pop r15
reti
; @end
; ---------------------------------------------------------------------------
; @routine ComOnUart0_TxCharIsr @global @isr
;
; @clobbers none
ComOnUart0_TxCharIsr:
push r15
in r15, SREG
push r16
push r17
push yl
push yh
ldi yl, LOW(comOnUart0_iface)
ldi yh, HIGH(comOnUart0_iface)
rcall comOnUart0TxCharIsr ; (R16, R17)
pop yh
pop yl
pop r17
pop r16
out SREG, r15
pop r15
reti
; @end
; --------------------------------------------------------------------------- ; ---------------------------------------------------------------------------
; @routine ComOnUart0AttnChangeIsr @global @isr ; @routine ComOnUart0AttnChangeIsr @global @isr
; ;
@@ -707,7 +603,7 @@ comOnUart0ActOnAttn_end:
; @routine comOnUart0RxCharIsr @global ; @routine comOnUart0RxCharIsr @global
; ;
; @param Y pointer to interface data in SRAM ; @param Y pointer to interface data in SRAM
; @clobbers R16, R17, R18, R24, R25, X ; @clobbers R16, R17, R18, R19, R20, R24, R25, X, Z
comOnUart0RxCharIsr: comOnUart0RxCharIsr:
; check for errors ; check for errors
@@ -749,8 +645,8 @@ comOnUart0RxCharIsr:
brne comOnUart0RxCharIsr_end ; jmp if still bytes left to receive brne comOnUart0RxCharIsr_end ; jmp if still bytes left to receive
comOnUart0RxCharIsr_complete: comOnUart0RxCharIsr_complete:
rcall comOnUart0StopRx rcall comOnUart0StopRx
ldi r16, UART_HW2_MODE_MSGRECEIVED rcall comOnUart0HandleMsgReceived ; (R16, R17, R18, R19, R20, R24, R25, X, Z)
rcall comOnUart0SetMode ; (R17)
rjmp comOnUart0RxCharIsr_end rjmp comOnUart0RxCharIsr_end
comOnUart0RxCharIsr_hwerr: comOnUart0RxCharIsr_hwerr:
ldi r16, NET_IFACE_OFFS_ERR_IO_LOW ldi r16, NET_IFACE_OFFS_ERR_IO_LOW
@@ -772,76 +668,54 @@ comOnUart0RxCharIsr_end:
; --------------------------------------------------------------------------- ; ---------------------------------------------------------------------------
; @routine comOnUart0TxUdreIsr @global ; @routine comOnUart0SendMsg
; ;
; Handler for UDRE1 interrupt called when TX data register is empty. ; @param Y pointer to interface data in SRAM
; ; @param X pointer to buffer to send
; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_MODE) ; @return CFLAG set if writing started, cleared otherwise
; @clobbers R16, R17, X ; @clobbers R16, R17, X (R22, R24, R25)
comOnUart0TxUdreIsr: comOnUart0SendMsg:
inr r16, UCSR0A rcall comOnUart0AcquireAttn ; (R22)
sbrs r16, UDRE0 brcc comOnUart0SendMsg_ebusy
rjmp comOnUart0TxUdreIsr_disable_irq ; not ready adiw xh:xl, NETMSG_OFFS_MSGLEN
; check bytes left ld r17, X
ldd r17, Y+UART_HW2_IFACE_OFFS_BUFLEFT sbiw xh:xl, NETMSG_OFFS_MSGLEN
tst r17 subi r17, -3 ; add dest addr, msglen, crc
breq comOnUart0TxUdreIsr_finished rcall comOnUart0StartTx ; (R16)
; read byte ; TODO: check size!
ldd xl, Y+UART_HW2_IFACE_OFFS_BUFPOS_LOW ; r17=number of bytes to write, X=buffer
ldd xh, Y+UART_HW2_IFACE_OFFS_BUFPOS_HIGH comOnUart0SendMsg_loop:
ld r16, X+ ; wait until transceiver ready
std Y+UART_HW2_IFACE_OFFS_BUFPOS_LOW, xl inr r16, UCSR0A
std Y+UART_HW2_IFACE_OFFS_BUFPOS_HIGH, xh sbrs r16, UDRE0
; send byte rjmp comOnUart0SendMsg_loop
outr UDR0, r16 ; send byte ; clear TXC flag by sending a 1
; decreased counter sbr r16, (1<<TXC0)
dec r17 outr UCSR0A, r16
std Y+UART_HW2_IFACE_OFFS_BUFLEFT, r17 ; write byte to uart data register
brne comOnUart0TxUdreIsr_end ; still bytes left to send, jump ld r16, X+
comOnUart0TxUdreIsr_finished: outr UDR0, r16
ldi r16, UART_HW2_MODE_WAITBUFFEREMPTY dec r17
rcall comOnUart0SetMode ; (R17) brne comOnUart0SendMsg_loop
comOnUart0TxUdreIsr_disable_irq: ; wait until all data send (i.e. send buffer empty and all bits shifted out)
; disable further DRE interrupts comOnUart0SendMsg_loopComplete:
inr r16, UCSR0B inr r16, UCSR0A
cbr r16, (1<<UDRIE0) ; disable TX data register empty interrupt sbrs r16, TXC0
outr UCSR0B, r16 rjmp comOnUart0SendMsg_loopComplete
comOnUart0TxUdreIsr_end: rcall comOnUart0StopTx ; (R16)
rcall comOnUart0SetAttnInput ; release ATTN (none)
rcall Utils_WaitFor10MicroSecs ; make sure ATTN is at least high for a short period (R22)
sec
rjmp comOnUart0SendMsg_end
comOnUart0SendMsg_ebusy:
ldi r16, NET_IFACE_OFFS_ERR_BUSY_LOW
rcall NET_Interface_IncCounter16 ; (R24, R25)
clc
comOnUart0SendMsg_end:
ret ret
; @end ; @end
; ---------------------------------------------------------------------------
; @routine comOnUart0TxCharIsr @global
;
; Handler for TXC0 interrupt called when the last byte has been completely sent and
; the data register is empty.
;
; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_MODE)
; @clobbers R16, R17
comOnUart0TxCharIsr:
; disable further TXC interrupts
inr r16, UCSR0B
cbr r16, (1<<TXCIE0) ; disable TXC1 interrupt
outr UCSR0B, r16
rcall comOnUart0StopTx ; (R16)
ldi r16, UART_HW2_MODE_MSGSENT
rcall comOnUart0SetMode ; (R17)
ret
; @end
#endif ; AVR_MODULES_UART_HW2_COMONUART0_H #endif ; AVR_MODULES_UART_HW2_COMONUART0_H

View File

@@ -33,21 +33,12 @@ ComOnUart1_Init:
ldi yl, LOW(comOnUart1_iface) ldi yl, LOW(comOnUart1_iface)
ldi yh, HIGH(comOnUart1_iface) ldi yh, HIGH(comOnUart1_iface)
rcall NET_Interface_Init ; (R16, R17, X) rcall NET_Interface_Init ; (R16, R17, X)
ldi r16, 0xff
std Y+UART_HW2_IFACE_OFFS_WRITEBUFNUM, r16
ldi r16, UART_HW2_MODE_IDLE ldi r16, UART_HW2_MODE_IDLE
std Y+UART_HW2_IFACE_OFFS_MODE, r16 std Y+UART_HW2_IFACE_OFFS_MODE, r16
clr r16 clr r16
std Y+NET_IFACE_OFFS_IFACENUM, r16 std Y+NET_IFACE_OFFS_IFACENUM, r16
rcall comOnUart1SetAttnInput rcall comOnUart1SetAttnInput
.ifdef COM_ATTN1_PUE
inr r16, COM_ATTN1_PUE
cbr r16, (1<<COM_ATTN1_PIN)
outr COM_ATTN1_PUE, r16
.endif
inr r16, COM_IRQ_ADDR_ATTN1 inr r16, COM_IRQ_ADDR_ATTN1
sbr r16, (1<<COM_IRQ_BIT_ATTN1) ; enable pin change irq for ATTN line sbr r16, (1<<COM_IRQ_BIT_ATTN1) ; enable pin change irq for ATTN line
outr COM_IRQ_ADDR_ATTN1, r16 outr COM_IRQ_ADDR_ATTN1, r16
@@ -153,84 +144,12 @@ comOnUart1StartReading:
; ---------------------------------------------------------------------------
; @routine comOnUart1StartWriting
;
; @param Y pointer to interface data in SRAM
; @param R16 buffer number
; @return CFLAG set if writing started, cleared otherwise
; @clobbers R16, R17, X, Z (R22, R24, R25)
comOnUart1StartWriting:
push r15
inr r15, SREG
cli
rcall comOnUart1StartWriting_noIrq
brcc comOnUart1StartWriting_clc
outr SREG, r15
pop r15
sec
ret
comOnUart1StartWriting_clc:
outr SREG, r15
pop r15
clc
ret
comOnUart1StartWriting_noIrq:
rcall comOnUart1AcquireAttn ; (R22)
brcc comOnUart1StartWriting_ebusy
; copy buffer
rcall NET_Buffer_Locate ; (R17)
std Y+UART_HW2_IFACE_OFFS_WRITEBUFNUM, r16
adiw xh:xl, NETMSG_OFFS_MSGLEN+1
ld r17, X
sbiw xh:xl, NETMSG_OFFS_MSGLEN+1
subi r17, -3 ; add dest addr, msglen, crc
; TODO: check size!
std Y+UART_HW2_IFACE_OFFS_BUFUSED, r17
std Y+UART_HW2_IFACE_OFFS_BUFLEFT, r17
; copy into IFACE buffer
mov zl, yl
mov zh, yh
adiw zh:zl, UART_HW2_IFACE_OFFS_BUFFER ; dest
std Y+UART_HW2_IFACE_OFFS_BUFPOS_LOW, zl
std Y+UART_HW2_IFACE_OFFS_BUFPOS_HIGH, zh
adiw xh:xl, 1 ; src (skip buffer header)
comOnUart1StartWriting_loop:
ld r16, X+
st Z+, r16
dec r17
brne comOnUart1StartWriting_loop
ldi r16, UART_HW2_MODE_WRITING
rcall comOnUart1SetMode ; (R17)
rcall comOnUart1StartTx ; should be the last call here (R16)
sec
rjmp comOnUart1StartWriting_end
comOnUart1StartWriting_ebusy:
ldi r16, NET_IFACE_OFFS_ERR_BUSY_LOW
rcall NET_Interface_IncCounter16 ; (R24, R25)
clc
comOnUart1StartWriting_end:
ret
; @end
; --------------------------------------------------------------------------- ; ---------------------------------------------------------------------------
; @routine ComOnUart1_Run @global ; @routine ComOnUart1_Run @global
; ;
; @clobbers all ; @clobbers all
ComOnUart1_Run: ComOnUart1_Run:
push r15
inr r15, SREG
cli
rcall ComOnUart1_Run_noirq
outr SREG, r15
pop r15
ret
ComOnUart1_Run_noirq:
ldi yl, LOW(comOnUart1_iface) ldi yl, LOW(comOnUart1_iface)
ldi yh, HIGH(comOnUart1_iface) ldi yh, HIGH(comOnUart1_iface)
ldd r16, Y+UART_HW2_IFACE_OFFS_MODE ldd r16, Y+UART_HW2_IFACE_OFFS_MODE
@@ -269,10 +188,7 @@ comOnUart1ModeJumpTable:
rjmp comOnUart1RunIdle rjmp comOnUart1RunIdle
rjmp comOnUart1RunReading rjmp comOnUart1RunReading
rjmp comOnUart1RunSkipping rjmp comOnUart1RunSkipping
rjmp comOnUart1RunMsgReceived
rjmp comOnUart1RunWriting rjmp comOnUart1RunWriting
rjmp comOnUart1RunWaitBufferEmpty
rjmp comOnUart1RunMsgSent
; @end ; @end
@@ -281,15 +197,48 @@ comOnUart1ModeJumpTable:
; @routine comOnUart1RunIdle ; @routine comOnUart1RunIdle
; ;
; @param Y pointer to interface data in SRAM ; @param Y pointer to interface data in SRAM
; @clobbers R16, R17, R24, R25, X, Z ; @clobbers R16, R17, R22, R24, R25, X
comOnUart1RunIdle: comOnUart1RunIdle:
; look for outbound message push r15
rcall NET_Interface_PeekNextOutgoingMsgNum ; r16=msgNum inr r15, SREG
brcc comOnUart1RunIdle_end ; no outmsg in queue cli
rcall comOnUart1StartWriting ; (R16, R17, R22, R24, R25, X, Z) ; look for outbound message
rcall NET_Interface_PeekNextOutgoingMsgNum ; r16=msgNum
brcs comOnUart1RunIdle_haveMsg
out SREG, r15
pop r15
rjmp comOnUart1RunIdle_end
comOnUart1RunIdle_haveMsg:
mov r24, r16
ldi r16, UART_HW2_MODE_WRITING
rcall comOnUart1SetMode ; (R17)
mov r16, r24
out SREG, r15
pop r15
push r16
rcall NET_Buffer_Locate ; (R17)
adiw xh:xl, 1
rcall comOnUart1SendMsg ; (R16, R17, R22, R24, R25, X)
push r15
inr r15, SREG ; save SREG (no CLI, we want to save CFLAG only)
ldi r16, UART_HW2_MODE_IDLE
rcall comOnUart1SetMode ; (R17)
out SREG, r15 ; restore SREG
pop r15
pop r16
brcc comOnUart1RunIdle_end brcc comOnUart1RunIdle_end
rcall NET_Interface_GetNextOutgoingMsgNum ; take current msg off the queue
push r15
inr r15, SREG
cli
rcall NET_Interface_GetNextOutgoingMsgNum ; take current msg off the queue
rcall NET_Buffer_ReleaseByNum ; (R16, X)
out SREG, r15
pop r15
sec
comOnUart1RunIdle_end: comOnUart1RunIdle_end:
ret ret
; @end ; @end
@@ -326,12 +275,12 @@ comOnUart1RunSkipping_end:
; --------------------------------------------------------------------------- ; ---------------------------------------------------------------------------
; @routine comOnUart1RunMsgReceived ; @routine comOnUart1HandleMsgReceived
; ;
; @param Y pointer to interface data in SRAM ; @param Y pointer to interface data in SRAM
; @clobbers R16, R17, R18, X, Z (R19, R20, R24, R25) ; @clobbers R16, R17, R18, X, Z (R19, R20, R24, R25)
comOnUart1RunMsgReceived: comOnUart1HandleMsgReceived:
mov xl, yl mov xl, yl
mov xh, yh mov xh, yh
adiw xh:xl, UART_HW2_IFACE_OFFS_BUFFER adiw xh:xl, UART_HW2_IFACE_OFFS_BUFFER
@@ -389,42 +338,6 @@ comOnUart1RunWriting:
; ---------------------------------------------------------------------------
; @routine comOnUart1RunWaitBufferEmpty
;
; @clobbers none
comOnUart1RunWaitBufferEmpty:
; TODO: check for timeout etc.
ret
; @end
; ---------------------------------------------------------------------------
; @routine comOnUart1RunWriting
;
; @param Y pointer to interface data in SRAM
; @clobbers R16 (R17, R22, R24, R25, X)
comOnUart1RunMsgSent:
ldd r16, Y+UART_HW2_IFACE_OFFS_WRITEBUFNUM
rcall NET_Buffer_ReleaseByNum ; (R16, X)
ldi r16, 0xff
std Y+UART_HW2_IFACE_OFFS_WRITEBUFNUM, r16
ldi r16, NET_IFACE_OFFS_PACKETSOUT_LOW
rcall NET_Interface_IncCounter16 ; (R24, R25)
ldi r16, UART_HW2_MODE_IDLE
rcall comOnUart1SetMode ; (R17)
rcall comOnUart1SetAttnInput ; release ATTN (none)
rcall Utils_WaitFor10MicroSecs ; make sure ATTN is at least high for a short period (R22)
ret
; @end
; --------------------------------------------------------------------------- ; ---------------------------------------------------------------------------
; @routine comOnUart1AcquireAttn ; @routine comOnUart1AcquireAttn
; ;
@@ -485,10 +398,11 @@ comOnUart1StopRx:
comOnUart1StartTx: comOnUart1StartTx:
inr r16, UCSR1A inr r16, UCSR1A
cbr r16, (1<<TXC1) ; clear TXCn interrupt cbr r16, (1<<TXC1) ; clear TXCn interrupt
outr UCSR1A, r16 outr UCSR1A, r16
inr r16, UCSR1B inr r16, UCSR1B
sbr r16, (1<<UDRIE1) | (1<<TXCIE1) | (1<<TXEN1) ; enable TX UDRE and TXC0 interrupt, enable transceive cbr r16, (1<<UDRIE1) | (1<<TXCIE1) ; disable TX UDRE and TXC0 interrupt, enable transceive
sbr r16, (1<<TXEN1) ; enable TX UDRE and TXC0 interrupt, enable transceive
outr UCSR1B, r16 outr UCSR1B, r16
ret ret
; @end ; @end
@@ -502,7 +416,7 @@ comOnUart1StartTx:
comOnUart1StopTx: comOnUart1StopTx:
inr r16, UCSR1B inr r16, UCSR1B
cbr r16, (1<<UDRIE1) | (1<<TXCIE1) | (1<<TXEN1) ; disable TX UDRE and TXC0 interrupt, enable transceive cbr r16, (1<<UDRIE1) | (1<<TXCIE1) | (1<<TXEN1) ; disable TX UDRE and TXC0 interrupt, disable transceive
outr UCSR1B, r16 outr UCSR1B, r16
ret ret
; @end ; @end
@@ -520,10 +434,17 @@ comOnUart1StopTx:
comOnUart1SetAttnInput: comOnUart1SetAttnInput:
cbi COM_ATTN1_DDR, COM_ATTN1_PIN ; set ATTN as input cbi COM_ATTN1_DDR, COM_ATTN1_PIN ; set ATTN as input
.ifdef COM_ATTN1_PUE .ifdef COM_ATTN1_PUE
; cbi COM_ATTN1_PUE, COM_ATTN_PIN ; disable pullup on ATTN ; cbi COM_ATTN1_PUE, COM_ATTN_PIN ; disable pullup on ATTN
.else .else
cbi COM_ATTN1_OUTPUT, COM_ATTN1_PIN ; disable pullup on ATTN cbi COM_ATTN1_OUTPUT, COM_ATTN1_PIN ; disable pullup on ATTN
.endif .endif
push r16
inr r16, COM_IRQ_ADDR_ATTN1
sbr r16, (1<<COM_IRQ_BIT_ATTN1) ; enable pin change irq for ATTN line
outr COM_IRQ_ADDR_ATTN1, r16
pop r16
ret ret
; @end ; @end
@@ -537,8 +458,13 @@ comOnUart1SetAttnInput:
; @clobbers none ; @clobbers none
comOnUart1SetAttnLow: comOnUart1SetAttnLow:
sbi COM_ATTN1_DDR, COM_ATTN1_PIN ; set ATTN as output push r16
cbi COM_ATTN1_OUTPUT, COM_ATTN1_PIN ; set ATTN low inr r16, COM_IRQ_ADDR_ATTN1
cbr r16, (1<<COM_IRQ_BIT_ATTN1) ; disable pin change irq for ATTN line
outr COM_IRQ_ADDR_ATTN1, r16
pop r16
sbi COM_ATTN1_DDR, COM_ATTN1_PIN ; set ATTN as output
cbi COM_ATTN1_OUTPUT, COM_ATTN1_PIN ; set ATTN low
ret ret
; @end ; @end
@@ -570,21 +496,29 @@ ComOnUart1_RxCharIsr:
push r16 push r16
push r17 push r17
push r18 push r18
push r24 push r19
push r25 push r20
push xl push r24
push xh push r25
push yl push xl
push yh push xh
ldi yl, LOW(comOnUart1_iface) push yl
ldi yh, HIGH(comOnUart1_iface) push yh
rcall comOnUart1RxCharIsr ; (R16, R17, R18, R24, R25, X) push zl
pop yh push zh
pop yl ldi yl, LOW(comOnUart1_iface)
pop xh ldi yh, HIGH(comOnUart1_iface)
pop xl rcall comOnUart1RxCharIsr ; (R16, R17, R18, R19, R20, R24, R25, X, Z)
pop r25 pop zh
pop r24 pop zl
pop yh
pop yl
pop xh
pop xl
pop r25
pop r24
pop r20
pop r19
pop r18 pop r18
pop r17 pop r17
pop r16 pop r16
@@ -595,62 +529,6 @@ ComOnUart1_RxCharIsr:
; ---------------------------------------------------------------------------
; @routine ComOnUart1_TxUdreIsr @global @isr
;
; @clobbers none
ComOnUart1_TxUdreIsr:
push r15
in r15, SREG
push r16
push r17
push xl
push xh
push yl
push yh
ldi yl, LOW(comOnUart1_iface)
ldi yh, HIGH(comOnUart1_iface)
rcall comOnUart1TxUdreIsr ; (R16, R17, X)
pop yh
pop yl
pop xh
pop xl
pop r17
pop r16
out SREG, r15
pop r15
reti
; @end
; ---------------------------------------------------------------------------
; @routine ComOnUart1_TxCharIsr @global @isr
;
; @clobbers none
ComOnUart1_TxCharIsr:
push r15
in r15, SREG
push r16
push r17
push yl
push yh
ldi yl, LOW(comOnUart1_iface)
ldi yh, HIGH(comOnUart1_iface)
rcall comOnUart1TxCharIsr ; (R16, R17)
pop yh
pop yl
pop r17
pop r16
out SREG, r15
pop r15
reti
; @end
; --------------------------------------------------------------------------- ; ---------------------------------------------------------------------------
; @routine ComOnUart1AttnChangeIsr @global @isr ; @routine ComOnUart1AttnChangeIsr @global @isr
; ;
@@ -701,10 +579,10 @@ ComOnUart1_HandleAttnChange:
; @clobbers R16 (R17, X) ; @clobbers R16 (R17, X)
comOnUart1ActOnAttn: comOnUart1ActOnAttn:
ldd r16, Y+UART_HW2_IFACE_OFFS_MODE
rcall comOnUart1IsAttnLow ; (none) rcall comOnUart1IsAttnLow ; (none)
brcc comOnUart1ActOnAttn_attnHigh brcc comOnUart1ActOnAttn_attnHigh
; ATTN low ; ATTN low
ldd r16, Y+UART_HW2_IFACE_OFFS_MODE
cpi r16, UART_HW2_MODE_IDLE cpi r16, UART_HW2_MODE_IDLE
brne comOnUart1ActOnAttn_end ; not idle brne comOnUart1ActOnAttn_end ; not idle
rcall comOnUart1StartReading ; (R16, R17, X) rcall comOnUart1StartReading ; (R16, R17, X)
@@ -725,7 +603,7 @@ comOnUart1ActOnAttn_end:
; @routine comOnUart1RxCharIsr @global ; @routine comOnUart1RxCharIsr @global
; ;
; @param Y pointer to interface data in SRAM ; @param Y pointer to interface data in SRAM
; @clobbers R16, R17, R18, R24, R25, X ; @clobbers R16, R17, R18, R19, R20, R24, R25, X, Z
comOnUart1RxCharIsr: comOnUart1RxCharIsr:
; check for errors ; check for errors
@@ -767,8 +645,8 @@ comOnUart1RxCharIsr:
brne comOnUart1RxCharIsr_end ; jmp if still bytes left to receive brne comOnUart1RxCharIsr_end ; jmp if still bytes left to receive
comOnUart1RxCharIsr_complete: comOnUart1RxCharIsr_complete:
rcall comOnUart1StopRx rcall comOnUart1StopRx
ldi r16, UART_HW2_MODE_MSGRECEIVED rcall comOnUart1HandleMsgReceived ; (R16, R17, R18, R19, R20, R24, R25, X, Z)
rcall comOnUart1SetMode ; (R17)
rjmp comOnUart1RxCharIsr_end rjmp comOnUart1RxCharIsr_end
comOnUart1RxCharIsr_hwerr: comOnUart1RxCharIsr_hwerr:
ldi r16, NET_IFACE_OFFS_ERR_IO_LOW ldi r16, NET_IFACE_OFFS_ERR_IO_LOW
@@ -790,76 +668,54 @@ comOnUart1RxCharIsr_end:
; --------------------------------------------------------------------------- ; ---------------------------------------------------------------------------
; @routine comOnUart1TxUdreIsr @global ; @routine comOnUart1SendMsg
; ;
; Handler for UDRE1 interrupt called when TX data register is empty. ; @param Y pointer to interface data in SRAM
; ; @param X pointer to buffer to send
; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_MODE) ; @return CFLAG set if writing started, cleared otherwise
; @clobbers R16, R17, X ; @clobbers R16, R17, X (R22, R24, R25)
comOnUart1TxUdreIsr: comOnUart1SendMsg:
inr r16, UCSR1A rcall comOnUart1AcquireAttn ; (R22)
sbrs r16, UDRE1 brcc comOnUart1SendMsg_ebusy
rjmp comOnUart1TxUdreIsr_disable_irq ; not ready adiw xh:xl, NETMSG_OFFS_MSGLEN
; check bytes left ld r17, X
ldd r17, Y+UART_HW2_IFACE_OFFS_BUFLEFT sbiw xh:xl, NETMSG_OFFS_MSGLEN
tst r17 subi r17, -3 ; add dest addr, msglen, crc
breq comOnUart1TxUdreIsr_finished rcall comOnUart1StartTx ; (R16)
; read byte ; TODO: check size!
ldd xl, Y+UART_HW2_IFACE_OFFS_BUFPOS_LOW ; r17=number of bytes to write, X=buffer
ldd xh, Y+UART_HW2_IFACE_OFFS_BUFPOS_HIGH comOnUart1SendMsg_loop:
ld r16, X+ ; wait until transceiver ready
std Y+UART_HW2_IFACE_OFFS_BUFPOS_LOW, xl inr r16, UCSR1A
std Y+UART_HW2_IFACE_OFFS_BUFPOS_HIGH, xh sbrs r16, UDRE1
; send byte rjmp comOnUart1SendMsg_loop
outr UDR1, r16 ; send byte ; clear TXC flag by sending a 1
; decreased counter sbr r16, (1<<TXC1)
dec r17 outr UCSR1A, r16
std Y+UART_HW2_IFACE_OFFS_BUFLEFT, r17 ; write byte to uart data register
brne comOnUart1TxUdreIsr_end ; still bytes left to send, jump ld r16, X+
comOnUart1TxUdreIsr_finished: outr UDR1, r16
ldi r16, UART_HW2_MODE_WAITBUFFEREMPTY dec r17
rcall comOnUart1SetMode ; (R17) brne comOnUart1SendMsg_loop
comOnUart1TxUdreIsr_disable_irq: ; wait until all data send (i.e. send buffer empty and all bits shifted out)
; disable further DRE interrupts comOnUart1SendMsg_loopComplete:
inr r16, UCSR1B inr r16, UCSR1A
cbr r16, (1<<UDRIE1) ; disable TX data register empty interrupt sbrs r16, TXC1
outr UCSR1B, r16 rjmp comOnUart1SendMsg_loopComplete
comOnUart1TxUdreIsr_end: rcall comOnUart1StopTx ; (R16)
rcall comOnUart1SetAttnInput ; release ATTN (none)
rcall Utils_WaitFor10MicroSecs ; make sure ATTN is at least high for a short period (R22)
sec
rjmp comOnUart1SendMsg_end
comOnUart1SendMsg_ebusy:
ldi r16, NET_IFACE_OFFS_ERR_BUSY_LOW
rcall NET_Interface_IncCounter16 ; (R24, R25)
clc
comOnUart1SendMsg_end:
ret ret
; @end ; @end
; ---------------------------------------------------------------------------
; @routine comOnUart1TxCharIsr @global
;
; Handler for TXC0 interrupt called when the last byte has been completely sent and
; the data register is empty.
;
; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_MODE)
; @clobbers R16, R17
comOnUart1TxCharIsr:
; disable further TXC interrupts
inr r16, UCSR1B
cbr r16, (1<<TXCIE1) ; disable TXC1 interrupt
outr UCSR1B, r16
rcall comOnUart1StopTx ; (R16)
ldi r16, UART_HW2_MODE_MSGSENT
rcall comOnUart1SetMode ; (R17)
ret
; @end
#endif ; AVR_MODULES_UART_HW2_COMONUART1_H #endif ; AVR_MODULES_UART_HW2_COMONUART1_H

View File

@@ -17,23 +17,19 @@
.equ UART_HW2_MODE_IDLE = 0 .equ UART_HW2_MODE_IDLE = 0
.equ UART_HW2_MODE_READING = 1 .equ UART_HW2_MODE_READING = 1
.equ UART_HW2_MODE_SKIPPING = 2 .equ UART_HW2_MODE_SKIPPING = 2
.equ UART_HW2_MODE_MSGRECEIVED = 3 .equ UART_HW2_MODE_WRITING = 3
.equ UART_HW2_MODE_WRITING = 4 .equ UART_HW2_MODE_NUM = 4
.equ UART_HW2_MODE_WAITBUFFEREMPTY = 5
.equ UART_HW2_MODE_MSGSENT = 6
.equ UART_HW2_MODE_NUM = 7
.equ UART_HW2_IFACE_OFFS_BEGIN = NET_IFACE_SIZE .equ UART_HW2_IFACE_OFFS_BEGIN = NET_IFACE_SIZE
.equ UART_HW2_IFACE_OFFS_MODE = UART_HW2_IFACE_OFFS_BEGIN .equ UART_HW2_IFACE_OFFS_MODE = UART_HW2_IFACE_OFFS_BEGIN
.equ UART_HW2_IFACE_OFFS_MODECOUNTER = UART_HW2_IFACE_OFFS_BEGIN+1 .equ UART_HW2_IFACE_OFFS_MODECOUNTER = UART_HW2_IFACE_OFFS_BEGIN+1
.equ UART_HW2_IFACE_OFFS_WRITEBUFNUM = UART_HW2_IFACE_OFFS_BEGIN+2 .equ UART_HW2_IFACE_OFFS_BUFPOS_LOW = UART_HW2_IFACE_OFFS_BEGIN+2
.equ UART_HW2_IFACE_OFFS_BUFPOS_LOW = UART_HW2_IFACE_OFFS_BEGIN+3 .equ UART_HW2_IFACE_OFFS_BUFPOS_HIGH = UART_HW2_IFACE_OFFS_BEGIN+3
.equ UART_HW2_IFACE_OFFS_BUFPOS_HIGH = UART_HW2_IFACE_OFFS_BEGIN+4 .equ UART_HW2_IFACE_OFFS_BUFUSED = UART_HW2_IFACE_OFFS_BEGIN+4
.equ UART_HW2_IFACE_OFFS_BUFUSED = UART_HW2_IFACE_OFFS_BEGIN+5 .equ UART_HW2_IFACE_OFFS_BUFLEFT = UART_HW2_IFACE_OFFS_BEGIN+5
.equ UART_HW2_IFACE_OFFS_BUFLEFT = UART_HW2_IFACE_OFFS_BEGIN+6 .equ UART_HW2_IFACE_OFFS_BUFFER = UART_HW2_IFACE_OFFS_BEGIN+6
.equ UART_HW2_IFACE_OFFS_BUFFER = UART_HW2_IFACE_OFFS_BEGIN+7
.equ UART_HW2_IFACE_SIZE = UART_HW2_IFACE_OFFS_BUFFER+UART_HW2_BUFFER_SIZE .equ UART_HW2_IFACE_SIZE = UART_HW2_IFACE_OFFS_BUFFER+UART_HW2_BUFFER_SIZE