avr: added t04.
This commit is contained in:
Martin Preuss
150
avr/devices/t04/boot/boot.asm
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150
avr/devices/t04/boot/boot.asm
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; ***************************************************************************
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; Source file for base system node on AtTiny 84
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;
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; This is for the maintenance system (i.e. the flash loader).
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;
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; All definitions and changes should go into this file.
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; ***************************************************************************
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;.equ clock=1000000 ; Define the clock frequency
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.equ clock=8000000 ; Define the clock frequency
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.nolist
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.include "include/tn841def.inc" ; Define device ATtiny841
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.list
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.include "version.asm"
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.include "../defs.asm"
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.include "devices/all/defs.asm"
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.include "common/calls.asm"
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.include "common/utils_wait.asm"
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; ***************************************************************************
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; defines
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;#define COM_ACCEPT_ALL_DEST 1
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; ---------------------------------------------------------------------------
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; LED
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.equ LED_DDR = DDRB
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.equ LED_PORT = PORTB
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.equ LED_PIN = PINB
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.equ LED_PINNUM = PORTB2
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; ***************************************************************************
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; code segment
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.cseg
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.org 0x0000
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; ---------------------------------------------------------------------------
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; Reset and interrupt vectors
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rjmp main ; 1: RESET Reset vector use this for flashed system
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reti ; 2: INT0 External Interrupt Request 0
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reti ; 3: PCINT0 Pin Change Interrupt 0
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reti ; 4: PCINT1 Pin Change Interrupt 1
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reti ; 5: WDT Watchdog Time-out
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reti ; 6: TIM1_CAPT Timer/Counter1 Capture Event
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reti ; 7: TIM1_COMPA (OC1A) Timer/Counter1 Compare Match A
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reti ; 8: TIM1_COMPB (OC1B) Timer/Counter1 Compare Match B
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reti ; 9: TIM1_OVF (OVF1) Timer/Counter1 Overflow
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reti ; 10: TIM0_COMPA (OC0A) Timer/Counter0 Compare Match A
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reti ; 11: TIM0_COMPB (OC0B) Timer/Counter0 Compare Match B
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reti ; 12: TIM0_OVF (OVF0) Timer/Counter0 Overflow
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reti ; 13: ANA_COMP0 Analog Comparator 0
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reti ; 14: ADC_READY ADC Conversion Complete
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reti ; 15: EE_RDY (ERDY) EEPROM Ready
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reti ; 16: ANA_COMP1 Analog Comparator 1
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reti ; 17: TIM2_CAPT Timer/Counter2 Capture Event
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reti ; 18: TIM2_COMPA (OC2A) Timer/Counter2 Compare Match A
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reti ; 19: TIM2_COMPB (OC2B) Timer/Counter2 Compare Match B
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reti ; 20: TIM2_OVF (OVF2) Timer/Counter2 Overflow
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reti ; 21: SPI SPI Serial Transfer Complete
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reti ; 22: USART0_RXS USART0 Rx Start
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reti ; 23: USART0_RXC USART0 Rx Complete
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reti ; 24: USART0_DRE USART0 Data Register Empty
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reti ; 25: USART0_TXC USART0 Tx Complete
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reti ; 26: USART1_RXS USART1 Rx Start
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reti ; 27: USART1_RXC USART1 Rx Complete
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reti ; 28: USART1_DRE USART1 Data Register Empty
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reti ; 29: USART1_TXC USART1 Tx Complete
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reti ; 30: TWI Two-Wire-Interface
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reti ; 31: RESERVED reserved
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devInfoBlock: ; 12 bytes
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devInfoManufacturer: .db 'A', 'Q', 'U', 'A'
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devInfoId: .db DEVICEINFO_ID, 0
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devInfoVersion: .db DEVICEINFO_VERSION, DEVICEINFO_REVISION ; version, revision
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firmwareVersion: .db FIRMWARE_VARIANT_BOOT, FIRMWARE_VERSION_MAJOR
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.db FIRMWARE_VERSION_MINOR, FIRMWARE_VERSION_PATCHLEVEL
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firmwareStart:
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rjmp main ; will be overwritten when flashing
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; ***************************************************************************
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; main code
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.org BOOTLOADER_ADDR
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main:
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rjmp bootLoader ; this routine is in modules/bootloader/main.asm
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; ***************************************************************************
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; includes
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.include "common/utils_wait_fixed.asm"
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.include "common/utils_copy_from_flash.asm"
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.include "common/utils_copy_sdram.asm"
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.include "modules/flash/defs.asm"
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.include "modules/flash/eeprom.asm"
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.include "modules/flash/io.asm"
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.include "modules/flash/io_uart0.asm"
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.include "modules/flash/io_uart_all.asm"
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.include "modules/flash/flashxp.asm"
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.include "modules/flash/flash4p.asm"
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.include "modules/flash/flashprocess.asm"
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.include "modules/flash/wait.asm"
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.include "modules/bootloader/main.asm"
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.include "modules/network/msg/defs.asm"
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.include "modules/network/msg/crc.asm"
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systemSetSpeed:
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.if clock == 1000000
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ldi r17, 0xd8
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ldi r16, (1<<CLKPS1) | (1<<CLKPS0) ; SUT=0, CLKPS=0011b
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sts CCP, r17
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sts CLKPR, r16
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.endif
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.if clock == 8000000
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ldi r17, 0xd8
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clr r16 ; SUT=0, CLKPS=0
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sts CCP, r17
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sts CLKPR, r16
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.endif
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ret
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