From 7962ff6213dd49227967af9bceab6ab55c2c56fe Mon Sep 17 00:00:00 2001
From: Martin Preuss <martin@aquamaniac.de>
Date: Sat, 25 Jan 2025 12:52:24 +0100
Subject: [PATCH] uart_hw: added flush/skip routine.

---
 avr/modules/uart_hw/lowlevel_tty.asm | 113 +++++++++++++++++++++++++++
 1 file changed, 113 insertions(+)

diff --git a/avr/modules/uart_hw/lowlevel_tty.asm b/avr/modules/uart_hw/lowlevel_tty.asm
index a488ca5..8d270e6 100644
--- a/avr/modules/uart_hw/lowlevel_tty.asm
+++ b/avr/modules/uart_hw/lowlevel_tty.asm
@@ -111,6 +111,24 @@ UART_HW_TtyOn1_StopTx:
 
 
 
+; ---------------------------------------------------------------------------
+; @routine UART_HW_TtyOn1_RecvSkipMessage
+;
+; skip all receiption data until a data pause of about 10ms
+;
+; @clobbers r16
+
+UART_HW_TtyOn1_RecvSkipMessage:
+UART_HW_TtyOn1_RecvSkipMessage_loop:
+    rcall ttyOn1RecvFlush            ; (r16)
+    ; wait for a data pause of 10ms
+    rcall ttyOn1RecvByteWithin10ms   ; (r20, r22)
+  brcs UART_HW_TtyOn1_RecvSkipMessage_loop
+  ret
+; @end
+
+
+
 ; ---------------------------------------------------------------------------
 ; @routine UART_HW_TtyOn1_RxCharIsr @global
 ;
@@ -163,6 +181,101 @@ UART_HW_TtyOn1_TxCharIsr_end:
 
 
 
+; ---------------------------------------------------------------------------
+; @routine ttyOn1RecvFlush
+;
+; Flush receiption buffer.
+;
+; @clobbers r16
+
+ttyOn1RecvFlush:
+    lds r16, UCSR1A ; read status
+    sbrs r16, RXC1
+    ret
+    lds r16, UDR1   ; read data byte
+  rjmp ttyOn1RecvFlush
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine ttyOn1RecvByteWithin10ms
+;
+; Wait up to 10ms for incoming byte and read it.
+;
+; @return CFLAG set if okay (data available), cleared on error
+; @return r16 byte received (if CFLAG set)
+; @clobbers: r20, r22
+
+ttyOn1RecvByteWithin10ms:
+  rcall ttyOn1WaitForData10ms                   ; (R20, R22)
+  brcc ttyOn1RecvByteWithin10ms_end
+  lds r16, UCSR1A                              ; check for errors
+  andi r16, (1<<FE1) | (1<<DOR1) | (1<<UPE1)
+  brne ttyOn1RecvByteWithin10ms_error
+  lds r16, UDR1                                ; read data byte
+  sec
+  ret
+ttyOn1RecvByteWithin10ms_error:
+  clc
+ttyOn1RecvByteWithin10ms_end:
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine ttyOn1WaitForData10ms
+;
+; Wait for incoming data for max 10 milliseconds.
+;
+; @return CFLAG set if okay (data available), cleared on error
+; @clobbers: r20, r22
+
+ttyOn1WaitForData10ms:
+.if clock == 8000000
+  ldi r20, 80
+.endif
+.if clock == 1000000
+  ldi r20, 10
+.endif
+ttyOn1WaitForData10ms_loop:
+    push r20
+      rcall ttyOn1WaitForData1000Cycles  ; (r20, r22)
+    pop r20
+    brcs ttyOn1WaitForData10ms_gotit
+    dec r20
+  brne ttyOn1WaitForData10ms_loop
+  clc
+ttyOn1WaitForData10ms_gotit:
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine ttyOn1WaitForData1000Cycles
+;
+; Wait for incoming data for max 1000 clock cycles
+; (about 1ms at 1MHz, 0.125 at 8MHz)
+;
+; @return CFLAG set if okay (packet received), cleared on error
+; @clobbers: r20, r22
+
+ttyOn1WaitForData1000Cycles:
+  ldi r20, 140                         ; 1
+ttyOn1WaitForData_loop:
+    lds r22, UCSR1A                    ; 2
+    sbrc r22, RXC1                     ; 2/3
+      rjmp ttyOn1WaitForData_gotit     ; 2
+    dec r20                            ; 1
+  brne ttyOn1WaitForData_loop           ; 1/2  -> 7 per loop, max about 1000
+  clc                                  ; 1
+  ret                                  ; 4
+ttyOn1WaitForData_gotit:
+  sec                                  ; 1
+  ret                                  ; 4
+; @end