avr: more work on ardware uart code.
This commit is contained in:
Martin Preuss
222
avr/modules/uart_hw/m_lowlevel_uart.asm
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222
avr/modules/uart_hw/m_lowlevel_uart.asm
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; ***************************************************************************
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; copyright : (C) 2025 by Martin Preuss
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; email : martin@libchipcard.de
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;
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; ***************************************************************************
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; * This file is part of the project "AqHome". *
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; * Please see toplevel file COPYING of that project for license details. *
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; ***************************************************************************
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; ---------------------------------------------------------------------------
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; @macro M_UART_HW_Uart_Init
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;
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; @param %0 UART number ("0" for UART0)
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; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_STATE)
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; @clobbers R16, R17, X
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.macro M_UART_HW_Uart_Init
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rcall UART_HW_InterfaceInit
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; set baudrate
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.if clock == 8000000
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ldi r16, 25 ; (19.2Kb/s at 8MHz)
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ldi r17, 0
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.endif
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.if clock == 1000000
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ldi r16, 2 ; (19.2Kb/s at 1MHz)
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ldi r17, 0
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.endif
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sts UBRR@0H, r17
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sts UBRR@0L, r16
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; set character format
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ldi r16, (1<<USBS@0)|(3<<UCSZ@00)
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sts UCSR@0C, r16
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.endmacro
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; @end
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; ---------------------------------------------------------------------------
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; @macro M_UART_HW_Uart_StartRx
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;
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; @param %0 UART number ("0" for UART0)
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; @clobbers none
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.macro M_UART_HW_Uart_StartRx
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lds r16, UCSR@0B
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sbr r16, (1<<RXCIE@0) | (1<<RXEN@0) ; enable RX complete interrupt, enable receive
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sts UCSR@0B, r16
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.endmacro
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; @end
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; ---------------------------------------------------------------------------
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; @macro M_UART_HW_Uart_StopRx
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;
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; @param %0 UART number ("0" for UART0)
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; @clobbers R16
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.macro M_UART_HW_Uart_StopRx
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lds r16, UCSR@0B
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cbr r16, (1<<RXCIE@0 | (1<<RXEN@0)) ; disable RX complete interrupt, disable receive
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sts UCSR@0B, r16
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.endmacro
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; @end
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; ---------------------------------------------------------------------------
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; @macro M_UART_HW_Uart_StartTx
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;
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; @param %0 UART number ("0" for UART0)
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; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_STATE)
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; @clobbers R16
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.macro M_UART_HW_Uart_StartTx
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lds r16, UCSR@0A
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cbr r16, (1<<TXC@0) ; clear TXCn interrupt
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sts UCSR@0A, r16
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lds r16, UCSR@0B
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sbr r16, (1<<UDRIE@0) | (1<<TXC@0) | (1<<TXEN@0) ; enable TX UDRE and TXC1 interrupt, enable transceive
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sts UCSR@0B, r16
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.endmacro
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; @end
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; ---------------------------------------------------------------------------
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; @macro M_UART_HW_Uart_StopTx
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;
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; @param %0 UART number ("0" for UART0)
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; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_STATE)
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; @clobbers R16
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.macro M_UART_HW_Uart_StopTx
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lds r16, UCSR@0B
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cbr r16, (1<<UDRIE@0) | (1<<TXC@0) | (1<<TXEN@0) ; disable TX UDRE and TXC1 interrupt, enable transceive
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sts UCSR@0B, r16
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.endmacro
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; @end
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; ---------------------------------------------------------------------------
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; @macro M_UART_HW_Uart_Flush
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;
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; Flush receiption buffer.
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;
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; @param %0 UART number ("0" for UART0)
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; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_MODE)
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; @clobbers R16
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.macro M_UART_HW_Uart_Flush
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l_loop_%:
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lds r16, UCSR@0A
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sbrs r16, RXC@0
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rjmp l_end_%
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lds r16, UDR@0
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clr r16
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std Y+UART_HW_IFACE_OFFS_READTIMER, r16
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rjmp l_loop_%
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l_end_%:
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.endmacro
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; @end
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; ---------------------------------------------------------------------------
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; @macro M_UART_HW_Uart_RxCharIsr
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;
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; @param %0 UART number ("0" for UART0)
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; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_MODE)
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; @clobbers R16 (R17, R18, X)
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.macro M_UART_HW_Uart_RxCharIsr
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lds r16, UCSR@0A ; check for errors
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andi r16, (1<<FE@0) | (1<<DOR@0) | (1<<UPE@0)
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breq l_recv_% ; no error, receive next char
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ldd r16, Y+UART_HW_IFACE_OFFS_STATUS ; set error status
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ori r16, (1<<UART_HW_STATUS_HWERR_BIT) ; -> HWERR
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rjmp l_setStatusAndEnd_%
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l_recv_%:
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lds r16, UCSR@0A
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sbrs r16, RXC@0
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rjmp l_end_% ; no data
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lds r16, UDR@0
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rcall UART_HW_InterfaceWriteToReadBuffer ; (R17, R18, X)
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brcc l_overrun_%
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clr r16
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std Y+UART_HW_IFACE_OFFS_READTIMER, r16 ; reset read timer
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rjmp l_end_%
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l_overrun_%:
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ldd r16, Y+UART_HW_IFACE_OFFS_STATUS ; set overrun error
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ori r16, (1<<UART_HW_STATUS_OVERRUN_BIT) ; -> OVERRUN
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l_setStatusAndEnd_%:
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std Y+UART_HW_IFACE_OFFS_STATUS, r16
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l_end_%:
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.endmacro
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; @end
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; ---------------------------------------------------------------------------
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; @macro M_UART_HW_Uart_TxUdreIsr
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;
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; Handler for UDREn interrupt called when TX data register is empty.
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;
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; @param %0 UART number ("0" for UART0)
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; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_MODE)
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; @clobbers R16, (R17, R18, X)
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.macro M_UART_HW_Uart_TxUdreIsr
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lds r16, UCSR@0A
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sbrs r16,UDRE@0
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rjmp l_end_% ; not ready
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rcall UART_HW_InterfaceReadFromWriteBuffer ; (R17, R18, X)
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brcs l_send_% ; got a byte, go send
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; disable further DRE1 interrupts
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lds r16, UCSR@0B
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cbr r16, (1<<UDRIE@0) ; disable TX data register empty interrupt
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sts UCSR@0B, r16
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rjmp l_end_%
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l_send_%:
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sts UDR@0, r16
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clr r16
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std Y+UART_HW_IFACE_OFFS_WRITETIMER, r16 ; reset write timer
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l_end_%:
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.endmacro
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; @end
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; ---------------------------------------------------------------------------
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; @macro M_UART_HW_Uart_TxCharIsr
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;
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; Handler for TXCn interrupt called when a last byte has been completely sent and
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; the data register is empty..
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;
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; @param %0 UART number ("0" for UART0)
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; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_MODE)
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; @clobbers R16, (R17, R18, X)
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.macro M_UART_HW_Uart_TxCharIsr
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; disable further TXC1 interrupts
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lds r16, UCSR@0B
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cbr r16, (1<<TXC@0) ; disable TXC1 interrupt
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sts UCSR@0B, r16
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; set underrun status (TODO: maybe change this later)
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ldd r16, Y+UART_HW_IFACE_OFFS_STATUS ; set underrun error
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ori r16, (1<<UART_HW_STATUS_UNDERRUN_BIT)
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std Y+UART_HW_IFACE_OFFS_STATUS, r16
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.endmacro
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; @end
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