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avr: more work on ardware uart code.

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This commit is contained in:
Martin Preuss
2025-02-09 21:06:31 +01:00
parent 601559ca6e
commit 703f8042f9
8 changed files with 698 additions and 97 deletions
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107
avr/modules/uart_hw/lowlevel_uart1.asm
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@@ -20,26 +20,7 @@
; @clobbers R16, R17, X
UART_HW_Uart1_Init:
rcall UART_HW_InterfaceInit
; set baudrate
.if clock == 8000000
ldi r16, 25 ; (19.2Kb/s at 8MHz)
ldi r17, 0
.endif
.if clock == 1000000
ldi r16, 2 ; (19.2Kb/s at 1MHz)
ldi r17, 0
.endif
sts UBRR1H, r17
sts UBRR1L, r16
; set character format
ldi r16, (1<<USBS1)|(3<<UCSZ10)
sts UCSR1C, r16
M_UART_HW_Uart_Init 1
ret
; @end
@@ -51,9 +32,7 @@ UART_HW_Uart1_Init:
; @clobbers none
UART_HW_Uart1_StartRx:
lds r16, UCSR1B
sbr r16, (1<<RXCIE1) | (1<<RXEN1) ; enable RX complete interrupt, enable receive
sts UCSR1B, r16
M_UART_HW_Uart_StartRx 1
ret
; @end
@@ -65,9 +44,7 @@ UART_HW_Uart1_StartRx:
; @clobbers R16
UART_HW_Uart1_StopRx:
lds r16, UCSR1B
cbr r16, (1<<RXCIE1 | (1<<RXEN1)) ; disable RX complete interrupt, disable receive
sts UCSR1B, r16
M_UART_HW_Uart_StopRx 1
ret
; @end
@@ -80,9 +57,7 @@ UART_HW_Uart1_StopRx:
; @clobbers R16
UART_HW_Uart1_StartTx:
lds r16, UCSR1B
sbr r16, (1<<UDRIE1) | (1<<TXEN1) ; enable TX data register empty interrupt, enable transceive
sts UCSR1B, r16
M_UART_HW_Uart_StartTx 1
ret
; @end
@@ -95,9 +70,21 @@ UART_HW_Uart1_StartTx:
; @clobbers R16
UART_HW_Uart1_StopTx:
lds r16, UCSR1B
cbr r16, (1<<UDRIE1) | (1<<TXEN1) ; disable TX data register empty interrupt, disable transceive
sts UCSR1B, r16
M_UART_HW_Uart_StopTx 1
ret
; @end
; ---------------------------------------------------------------------------
; @routine UART_HW_Uart1_Flush
;
; Flush receiption buffer.
;
; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_MODE)
; @clobbers R16
UART_HW_Uart1_Flush:
M_UART_HW_Uart_Flush 1
ret
; @end
@@ -110,24 +97,22 @@ UART_HW_Uart1_StopTx:
; @clobbers R16 (R17, R18, X)
UART_HW_Uart1_RxCharIsr:
lds r16, UCSR1A ; check for errors
andi r16, (1<<FE1) | (1<<DOR1) | (1<<UPE1)
breq UART_HW_Uart1_RxCharIsr_recv ; no error, receive next char
ldd r16, Y+UART_HW_IFACE_OFFS_STATUS ; set error status
ori r16, UART_HW_STATUS_HWERR ; -> HWERR
rjmp UART_HW_Uart1_RxCharIsr_setStatusAndEnd
UART_HW_Uart1_RxCharIsr_recv:
lds r16, UCSR1A
sbrs r16, RXC1
rjmp UART_HW_Uart1_RxCharIsr_end ; no data
lds r16, UDR1
rcall UART_HW_InterfaceWriteToReadBuffer ; (R17, R18, X)
brcs UART_HW_Uart1_RxCharIsr_end
ldd r16, Y+UART_HW_IFACE_OFFS_STATUS ; set overrun error
ori r16, UART_HW_STATUS_OVERRUN ; -> OVERRUN
UART_HW_Uart1_RxCharIsr_setStatusAndEnd:
std Y+UART_HW_IFACE_OFFS_STATUS, r16
UART_HW_Uart1_RxCharIsr_end:
M_UART_HW_Uart_RxCharIsr 1
ret
; @end
; ---------------------------------------------------------------------------
; @routine UART_HW_Uart1_TxUdreIsr @global
;
; Handler for UDRE1 interrupt called when TX data register is empty.
;
; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_MODE)
; @clobbers R16, (R17, R18, X)
UART_HW_Uart1_TxUdreIsr:
M_UART_HW_Uart_TxUdreIsr 1
ret
; @end
@@ -136,28 +121,14 @@ UART_HW_Uart1_RxCharIsr_end:
; ---------------------------------------------------------------------------
; @routine UART_HW_Uart1_TxCharIsr @global
;
; Handler for TXC1 interrupt called when a last byte has been completely sent and
; the data register is empty..
;
; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_MODE)
; @clobbers R16, (R17, R18, X)
UART_HW_Uart1_TxCharIsr:
lds r16, UCSR1A
sbrs r16,UDRE1
rjmp UART_HW_Uart1_TxCharIsr_end ; not ready
rcall UART_HW_InterfaceReadFromWriteBuffer ; (R17, R18, X)
brcs UART_HW_Uart1_TxCharIsr_send ; got a byte, go send
; disable further DRE1 interrupts
lds r16, UCSR1B
cbr r16, (1<<UDRIE1) ; disable TX data register empty interrupt
sts UCSR1B, r16
; set underrun status (TODO: maybe change this later)
ldd r16, Y+UART_HW_IFACE_OFFS_STATUS ; set underrun error
ori r16, UART_HW_STATUS_UNDERRUN
std Y+UART_HW_IFACE_OFFS_STATUS, r16
rjmp UART_HW_Uart1_TxCharIsr_end
UART_HW_Uart1_TxCharIsr_send:
sts UDR1, r16
UART_HW_Uart1_TxCharIsr_end:
M_UART_HW_Uart_TxCharIsr 1
ret
; @end