diff --git a/avr/att84_temp1.asm b/avr/att84_temp1.asm index d16633f..62500fc 100644 --- a/avr/att84_temp1.asm +++ b/avr/att84_temp1.asm @@ -21,12 +21,12 @@ ; AtTiny84 ; -------- ; VCC 1 14 GND -; PB0 2 13 PA0 +; PB0 2 13 PA0 REED_OUT ; PB1 3 12 PA1 COM-DATA -; /RESET PB3 4 11 PA2 [OWI] +; /RESET PB3 4 11 PA2 REED_IN1 ; [KEY1] PB2 5 10 PA3 LED ; COM_ATTN PA7 6 9 PA4 TWI-SCL -; TWI-SDA PA6 7 8 PA5 +; TWI-SDA PA6 7 8 PA5 REED_IN2 ; -------- ; ; *************************************************************************** @@ -67,6 +67,7 @@ ;#define MODULES_LCD #define MODULES_SI7021 #define MODULES_STATS +;#define MODULES_CNY70 .set MODULES_MASK = 0 @@ -91,6 +92,10 @@ #ifdef MODULES_STATS .set MODULES_MASK = MODULES_MASK | (1< bmp280 + cny70 com2 comproto flash diff --git a/avr/modules/cny70/0BUILD b/avr/modules/cny70/0BUILD new file mode 100644 index 0000000..febd367 --- /dev/null +++ b/avr/modules/cny70/0BUILD @@ -0,0 +1,11 @@ + + + + + + main.asm + + + + + diff --git a/avr/modules/cny70/main.asm b/avr/modules/cny70/main.asm new file mode 100644 index 0000000..8217f81 --- /dev/null +++ b/avr/modules/cny70/main.asm @@ -0,0 +1,182 @@ +; *************************************************************************** +; copyright : (C) 2023 by Martin Preuss +; email : martin@libchipcard.de +; +; *************************************************************************** +; * This file is part of the project "AqHome". * +; * Please see toplevel file COPYING of that project for license details. * +; *************************************************************************** + + +; doesn't work, yet + + + +; *************************************************************************** +; data + +.dseg + + +.equ CNY70_FLAGS_ADC_STARTED = 0x01 +.equ CNY70_FLAGS_ADC_FINISHED = 0x02 +.equ CNY70_FLAGS_ADC_VALID = 0x04 + +.equ CNY70_TIMER_100MS = 20 ; every 2s + + +cny70DataBegin: + cny70Flags: .byte 1 + cny70LastData: .byte 1 + cny70TimerCounter: .byte 1 +cny70DataEnd: + + + + +; *************************************************************************** +; code + +.cseg + + + +; --------------------------------------------------------------------------- +; Init module. +; +; IN: +; - nothing +; OUT: +; - CFLAG: set if okay, clear on error +; USED: + +CNY70_Init: + ; preset SRAM data area + ldi xh, HIGH(cny70DataBegin) + ldi xl, LOW(cny70DataBegin) + clr r16 + ldi r17, (cny70DataEnd-cny70DataBegin) + rcall Utils_FillSram + + ; setup pins and interrupts + sbi CNY70_DDR_LED, CNY70_PINNUM_LED ; set DATA port as output + cbi CNY70_PORT_LED, CNY70_PINNUM_LED ; LED off + cbi CNY70_PORT_ADC, CNY70_PINNUM_ADC ; disable internal pullup for ADC + cbi CNY70_DDR_ADC, CNY70_PINNUM_ADC ; set ADC port as input + + ldi r16, (1<