avr: some ideas for autosync.
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170
avr/modules/flash/io_softuart.asm
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170
avr/modules/flash/io_softuart.asm
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; ***************************************************************************
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; copyright : (C) 2025 by Martin Preuss
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; email : martin@libchipcard.de
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;
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; ***************************************************************************
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; * This file is part of the project "AqHome". *
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; * Please see toplevel file COPYING of that project for license details. *
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; ***************************************************************************
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.equ UARTSOFT_WAITFORSYNCSTART = 200
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; ***************************************************************************
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; code
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.cseg
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uartSoftWaitAndReadSyncByte:
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; wait for begin of startbit
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ldi r24, LOW(UARTSOFT_WAITFORSYNCSTART)
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ldi r25, HIGH(UARTSOFT_WAITFORSYNCSTART)
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uartSoftWaitAndReadSyncByte_loop0:
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sbis COM_DATA_INPUT, COM_DATA_PIN
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rjmp uartSoftWaitAndReadSyncByte_gotStartBit
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sbiw r25:r24, 1
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brne uartSoftWaitAndReadSyncByte_loop0
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uartSoftWaitAndReadSyncByte_error: ; timeout
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clc
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ret
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uartSoftWaitAndReadSyncByte_gotStartBit:
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clr r25
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clr r24
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; count cycles while DATA low (count length of startBit)
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uartSoftWaitAndReadSyncByte_loopLow: ; 5 cycles per loop +3 cycles to leave loop
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sbic COM_DATA_INPUT, COM_DATA_PIN ; +2 (skip)/+1 (no skip)
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rjmp uartSoftWaitAndReadSyncByte_startDataBit1 ; +0 (skip) / +2 (no skip)
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adiw r25:r24, 1 ; +1
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brne uartSoftWaitAndReadSyncByte_loopLow ; +2
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rjmp uartSoftWaitAndReadSyncByte_error
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uartSoftWaitAndReadSyncByte_startDataBit1:
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clr r25
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clr r24
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ldi r17, 4
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uartSoftWaitAndReadSyncByte_loopData:
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; count cycles while DATA high (count length of dataBit)
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uartSoftWaitAndReadSyncByte_loopDataHigh: ; 5 cycles per loop +3 cycles to leave loop
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sbis COM_DATA_INPUT, COM_DATA_PIN ; +2 (skip)/+1 (no skip)
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rjmp uartSoftWaitAndReadSyncByte_startLowDataBit ; +0 (skip) / +2 (no skip)
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adiw r25:r24, 1 ; +1
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brne uartSoftWaitAndReadSyncByte_loopDataHigh ; +2
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; too long LOW
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rjmp uartSoftWaitAndReadSyncByte_error
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uartSoftWaitAndReadSyncByte_startLowDataBit:
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; count cycles while DATA low (count length of dataBit)
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uartSoftWaitAndReadSyncByte_loopDataLow: ; 5 cycles per loop +3 cycles to leave loop
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sbic COM_DATA_INPUT, COM_DATA_PIN ; +2 (skip)/+1 (no skip)
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rjmp uartSoftWaitAndReadSyncByte_startHighDataBit ; +0 (skip) / +2 (no skip)
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adiw r25:r24, 1 ; +1
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brne uartSoftWaitAndReadSyncByte_loop4 ; +2
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; too long LOW
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rjmp uartSoftWaitAndReadSyncByte_error
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uartSoftWaitAndReadSyncByte_startHighDataBit:
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dec r17
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brne uartSoftWaitAndReadSyncByte_loopData
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; calc average (8 values)
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lsr r25 ; /2
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ror r24
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lsr r25 ; /4
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ror r24
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lsr r25 ; /8
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ror r24
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sec
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ret
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; @end
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uartSoftReceiveByte:
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; wait for begin of startbit
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ldi r24, LOW(UARTSOFT_WAITFORSYNCSTART)
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ldi r25, HIGH(UARTSOFT_WAITFORSYNCSTART)
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uartSoftReceiveByte_waitForBeginOfStartBit:
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sbis COM_DATA_INPUT, COM_DATA_PIN
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rjmp uartSoftReceiveByte_gotBeginOfStartBit
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sbiw r25:r24, 1
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brne uartSoftReceiveByte_waitForBeginOfStartBit
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uartSoftReceiveByte_error: ; timeout
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clc
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ret
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uartSoftReceiveByte_gotBeginOfStartBit:
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clr r25
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clr r24
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; count cycles while DATA low (count length of startBit)
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uartSoftReceiveByte_waitForEndOfStartBit: ; 5 cycles per loop
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sbic COM_DATA_INPUT, COM_DATA_PIN ; +2 (skip)/+1 (no skip)
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rjmp uartSoftReceiveByte_gotEndOfStartBit ; +0 (skip) / +2 (no skip)
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adiw r25:r24, 1 ; +1
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brne uartSoftWaitAndReadSyncByte_loopLow ; +2
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rjmp uartSoftReceiveByte_error
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uartSoftReceiveByte_gotEndOfStartBit:
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; r25:r24=counter equivalent for length of startbit
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clr r16
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ldi r17, 8
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uartSoftReceiveByte_bitLoop:
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; TODO: receive 8bits, wait for start of endbit
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ret
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uartSoftCountDataLow: ; 5 cycles per loop +5 cycles outside (+3 cycles RCALL)
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sbic COM_DATA_INPUT, COM_DATA_PIN ; +2 (skip)/+1 (no skip)
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rjmp uartSoftCountDataLow_ok ; +0 (skip) / +2 (no skip)
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adiw r25:r24, 1 ; +1
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brne uartSoftCountDataLow ; +2
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clc
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ret
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uartSoftCountDataLow_ok:
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sec
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ret
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; @end
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uartSoftCountDataHigh: ; 5 cycles per loop +5 cycles outside (+3 cycles RCALL)
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sbis COM_DATA_INPUT, COM_DATA_PIN ; +2 (skip)/+1 (no skip)
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rjmp uartSoftCountDataHigh_ok ; +0 (skip) / +2 (no skip)
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adiw r25:r24, 1 ; +1
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brne uartSoftCountDataHigh ; +2
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clc
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ret
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uartSoftCountDataHigh_ok:
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sec ; +1
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ret ; +4
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; @end
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uartSoftWaitBitTime: ; 5 cycles per loop +5 cycles outside (+3 cycles RCALL)
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uartSoftWaitBitTime_loop:
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nop ; +1
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nop ; +1
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sbiw r25:r24, 1 ; +1
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brne uartSoftWaitBitTime_loop ; +2
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nop ; +1
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ret ; +4
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; @end
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