From 40710a003ad55124d57bd52330cd90ce6afbae2b Mon Sep 17 00:00:00 2001 From: Martin Preuss Date: Sat, 4 Feb 2023 16:00:50 +0100 Subject: [PATCH] Utils: Added pseudo random generator. --- avr/utils.asm | 185 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 185 insertions(+) diff --git a/avr/utils.asm b/avr/utils.asm index 60f361b..0ea7d23 100644 --- a/avr/utils.asm +++ b/avr/utils.asm @@ -1,5 +1,9 @@ +; *************************************************************************** +; macros + + ; --------------------------------------------------------------------------- ; Utils_WaitNanoSecs waittime_in_ns , cyles_already_used , waitcount_register @@ -42,6 +46,81 @@ +; *************************************************************************** +; data + + +.dseg + +utilsDataBegin: + utilsSeed: .byte 2 +utilsDataEnd: + + + +; *************************************************************************** +; code + + +.cseg + +utilsDateString: .db "%YEAR%-%MONTH%-%DAY%-%HOUR%:%MINUTE%", 0, 0 + + + + +; --------------------------------------------------------------------------- +; Utils_Init +; +; IN: +; OUT: +; - CFLAG: set if okay, clear on error +; USED: R16, R17, R18, X, Y + +Utils_Init: + ; preset SRAM data area + ldi xh, HIGH(utilsDataBegin) + ldi xl, LOW(utilsDataBegin) + clr r16 + ldi r17, (utilsDataEnd-utilsDataBegin) + rcall Utils_FillSram + + ; generate initial seed from compile date string + ldi zl, LOW(utilsDateString*2) + ldi zh, HIGH(utilsDateString*2) + ldi r18, 0xe1 + ldi r19, 0xac +Utils_Init_l1: + lpm r16, Z+ + tst r16 + breq Utils_Init_l2 + eor r18, r16 + lsl r18 + rol r19 + rjmp Utils_Init_l1 +Utils_Init_l2: + sts utilsSeed, r18 + sts utilsSeed+1, r19 + + sec + ret + + + +; --------------------------------------------------------------------------- +; Utils_Fini +; +; IN: +; OUT: +; - CFLAG: set if okay, clear on error +; USED: R16, R17, R18, X, Y + + +Utils_Fini: + sec + ret + + ; --------------------------------------------------------------------------- ; Utils_FillSram @@ -263,3 +342,109 @@ wait: ; wait for possibly previous SPM to complete +; --------------------------------------------------------------------------- +; Utils_PseudoRandom +; +; Generate a pseudo random number. +; (see https://www.avrfreaks.net/s/topic/a5C3l000000URNfEAO/t119045?comment=P-1021038) +; +; IN: +; OUT: +; - R16: 8 bit pseudo random number +; REGS: R16, R17, R18, R19 + +Utils_PseudoRandom: + lds r16, utilsSeed + lds r17, utilsSeed+1 + ldi r18, 0x9c + ldi r19, 8 +Utils_PseudoRandom_step: + lsr r17 + ror r16 + brcc Utils_PseudoRandom_nomask + eor r17, r18 +Utils_PseudoRandom_nomask: + dec r19 + brne Utils_PseudoRandom_step + sts utilsSeed, r16 + sts utilsSeed+1, r17 + ret ; result in r16 + + + +; --------------------------------------------------------------------------- +; Utils_ReadUid +; +; Read UID from EEPROM. +; +; IN: +; OUT: +; - R18:R19:R20:R21: UID +; REGS: R16, X + +Utils_ReadUid: + push r15 + in r15, SREG + cli + ldi xl, LOW(EEPROM_OFFS_UUID) + ldi xh, HIGH(EEPROM_OFFS_UUID) + rcall Utils_ReadEeprom ; (R16) + mov r18, r16 + adiw xh:xl, 1 + rcall Utils_ReadEeprom ; (R16) + mov r19, r16 + adiw xh:xl, 1 + rcall Utils_ReadEeprom ; (R16) + mov r20, r16 + adiw xh:xl, 1 + rcall Utils_ReadEeprom ; (R16) + mov r21, r16 + pop r15 + out SREG, r15 + ret + + + +; --------------------------------------------------------------------------- +; Utils_SetupUid +; +; Reads UID from EEPROM. If not set generate a new one and store it in EEPROM. +; +; IN: +; OUT: +; - CFLAG set if new generated, cleared if there already was one. +; REGS: R15, R16, R18, R19, R20, R21, X + +Utils_SetupUid: + in r15, SREG + cli + rcall Utils_ReadUid ; R16, X + mov r16, r18 ; all 0xff? + or r16, r19 + or r16, r20 + or r16, r21 + breq Utils_SetupUid_generate ; yep, go generate one + out SREG, r15 + clc + ret +Utils_SetupUid_generate: + ldi xl, LOW(EEPROM_OFFS_UUID) + ldi xh, HIGH(EEPROM_OFFS_UUID) + rcall Utils_PseudoRandom ; byte 0 (R16, R17, R18, R19) + inc r16 + rcall Utils_WriteEeprom ; (R17) + adiw xh:xl, 1 + rcall Utils_PseudoRandom ; byte 1 + rcall Utils_WriteEeprom + adiw xh:xl, 1 + rcall Utils_PseudoRandom ; byte 2 + rcall Utils_WriteEeprom + adiw xh:xl, 1 + rcall Utils_PseudoRandom ; byte 3 + rcall Utils_WriteEeprom + adiw xh:xl, 1 + out SREG, r15 + sec + ret + +