From 3d1dd009114edb4788d6645e74322a575c11ec87 Mon Sep 17 00:00:00 2001
From: Martin Preuss <martin@aquamaniac.de>
Date: Mon, 30 Jan 2023 00:29:39 +0100
Subject: [PATCH] bmp280: started working on module.

---
 avr/bmp280.asm | 160 +++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 160 insertions(+)
 create mode 100644 avr/bmp280.asm

diff --git a/avr/bmp280.asm b/avr/bmp280.asm
new file mode 100644
index 0000000..4d63a77
--- /dev/null
+++ b/avr/bmp280.asm
@@ -0,0 +1,160 @@
+; ***************************************************************************
+; BMP280 module
+; (c) 2023 Martin Preuss
+;
+
+
+; ***************************************************************************
+; defines
+
+
+
+; ***************************************************************************
+; data
+
+.dseg
+
+bmp280DataBegin:
+  bmp280Id: .byte 1
+bmp280DataEnd:
+
+
+
+; ***************************************************************************
+; code
+
+.cseg
+
+
+
+
+; ---------------------------------------------------------------------------
+; BMP280_Init
+;
+; IN:
+; - nothing
+; OUT:
+; - CFLAG: set if okay, clear on error
+; USED:
+
+BMP280_Init:
+  ldi xh, HIGH(bmp280DataBegin)
+  ldi xl, LOW(bmp280DataBegin)
+  clr r16
+  ldi r17, (bmp280DataEnd-bmp280DataBegin)
+  rcall Utils_FillSram
+
+  rcall bmp280ReadId
+  brcc BMP280_Init_error
+  lds bmp280Id, r16    ; store id
+  push r16
+   rcall bmp280PrintDebug
+  pop r2           ; pop r16 into r2
+  ldi r16, 240
+  mov r1, r16
+  ldi r16, 0xff
+  rcall COM_EnqueueDebug
+  sec
+  ret
+BMP280_Init_error:
+  clc
+  ret
+
+
+; ---------------------------------------------------------------------------
+; BMP280_Fini
+;
+; IN:
+; - nothing
+; OUT:
+; - CFLAG: set if okay, clear on error
+; USED:
+
+BMP280_Fini:
+  sec
+  ret
+
+
+
+; ---------------------------------------------------------------------------
+; bmp280ReadId
+;
+; IN:
+; - nothing
+; OUT:
+; - CFLAG: set if okay, clear on error
+; - R16  : id (most probably 0x60)
+; USED: R15, R16 (R17, R18, R22)
+
+bmp280ReadId:
+  in r15, SREG
+  cli
+  rcall twiStart               ; (R22)
+  ldi r16, (BMP280_ADDR*2)     ; start in write mode
+  rcall twiSendByteExpectAck   ; (R16, R17, R18, R22)
+  brcc bmp280ReadId_error
+  ldi r16, 0xd0                ; register "id"
+  rcall twiSendByteExpectAck   ; (R16, R17, R18, R22)
+  brcc bmp280ReadId_error
+  rcall twiRestart             ; (R22)
+  ldi r16, (BMP280_ADDR*2)+1   ; restart in read mode
+  rcall twiSendByteExpectAck   ; (R16, R17, R18, R22)
+  brcc bmp280ReadId_error
+  
+  rcall twiReceiveByteSendAck  ; read ID
+  brcc bmp280ReadId_error
+  rcall twiStop                ; (R22)
+  out SREG, r15
+  sec
+  ret
+bmp280ReadId_error:
+  rcall twiStop                ; (R22)
+  out SREG, r15
+  clc
+  ret
+
+
+; ---------------------------------------------------------------------------
+; bmp280ReadRegsToSram
+;
+; IN:
+; - X: pointer to buffer to read data in
+; - R18: first register to read from
+; - R19: number of registers to read
+; OUT:
+; - CFLAG: set if okay, clear on error
+; - R16  : id (most probably 0x60)
+; USED: R15, R16 (R17, R18, R22)
+
+bmp280ReadRegsToSram:
+  in r15, SREG
+  cli
+  mov r1, r18
+  mov r2, r19
+  rcall twiStart                  ; (R22)
+  ldi r16, (BMP280_ADDR*2)        ; start in write mode
+  rcall twiSendByteExpectAck      ; (R16, R17, R18, R22)
+  brcc bmp280ReadRegsToSram_error
+
+  mov r16, r1                     ; first register to read
+  rcall twiSendByteExpectAck      ; (R16, R17, R18, R22)
+  brcc bmp280ReadRegsToSram_error
+  rcall twiRestart                ; (R22)
+  ldi r16, (BMP280_ADDR*2)+1      ; restart in read mode
+  rcall twiSendByteExpectAck      ; (R16, R17, R18, R22)
+  brcc bmp280ReadRegsToSram_error
+bmp280ReadRegsToSram_loop:
+    rcall twiReceiveByteSendAck   ; read register content
+    brcc bmp280ReadRegsToSram
+    dec r2
+  brne bmp280ReadRegsToSram_loop
+  rcall twiStop                   ; (R22)
+  out SREG, r15
+  sec
+  ret
+bmp280ReadRegsToSram_error:
+  rcall twiStop                ; (R22)
+  out SREG, r15
+  clc
+  ret
+