avr: t03 now at least writes tty message once!

avr/modules/uart_hw/m_lowlevel_uart.asm

@@ -138,6 +138,7 @@ l_end_%:
 ; @clobbers R16 (R17, R18, X)
 
 .macro M_UART_HW_Uart_RxCharIsr
+#if 0
   lds r16, UCSR@0A                              ; check for errors
   andi r16, (1<<FE@0) | (1<<DOR@0) | (1<<UPE@0)
   breq l_recv_%                                 ; no error, receive next char
@@ -160,6 +161,7 @@ l_overrun_%:
 l_setStatusAndEnd_%:
   std Y+UART_HW_IFACE_OFFS_STATUS, r16
 l_end_%:
+#endif
 .endmacro
 ; @end
 
@@ -172,24 +174,53 @@ l_end_%:
 ;
 ; @param %0 UART number ("0" for UART0)
 ; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_MODE)
-; @clobbers R16, (R17, R18, X)
+; @clobbers R16, R17, X
 
 .macro M_UART_HW_Uart_TxUdreIsr
   lds r16, UCSR@0A
   sbrs r16,UDRE@0
-    rjmp l_end_%                               ; not ready
-  rcall UART_HW_InterfaceReadFromWriteBuffer   ; (R17, R18, X)
-  brcs l_send_%                                ; got a byte, go send
+    rjmp l_disable_irq_%                       ; not ready
 
+  ; check write mode
+  ldd r16, Y+UART_HW_IFACE_OFFS_WRITEMODE
+  cpi r16, UART_HW_WRITEMODE_WRITING
+  brne l_disable_irq_%                         ; not in writing mode
+
+  ; check whether we have an active write buffer
+  ldd r16, Y+UART_HW_IFACE_OFFS_WRITEBUFNUM
+  cpi r16, 0xff
+  breq l_disable_irq_%                         ; no buffer
+
+  ; check whether there is data in the buffer to send
+  ldd r17, Y+UART_HW_IFACE_OFFS_WRITEBUFLEFT   ; r17=bytes left
+  tst r17
+  breq l_disable_irq_%                         ; nothing left to write
+  
+  ; get read ptr, read byte, inc read ptr, store ptr and bytesLeft
+  ldd xl, Y+UART_HW_IFACE_OFFS_WRITEBUFPOSLOW
+  ldd xh, Y+UART_HW_IFACE_OFFS_WRITEBUFPOSHIGH
+  ld r16, X+                                   ; r16=byte to write
+  std Y+UART_HW_IFACE_OFFS_WRITEBUFPOSLOW, xl
+  std Y+UART_HW_IFACE_OFFS_WRITEBUFPOSHIGH, xh
+  dec r17
+  std Y+UART_HW_IFACE_OFFS_WRITEBUFLEFT, r17
+  
+  ; send byte, reset write timer
+  sts UDR@0, r16
+  clr r16
+  std Y+UART_HW_IFACE_OFFS_WRITETIMER, r16     ; reset write timer
+  
+  ; still bytes left to write?
+  tst r17
+  brne l_end_%
+  ldi r16, UART_HW_WRITEMODE_WAITBUFFEREMPTY
+  std Y+UART_HW_IFACE_OFFS_WRITEMODE, r16      ; change mode to WAITBUFFEREMPTY
+
+l_disable_irq_%:
   ; disable further DRE1 interrupts
   lds r16, UCSR@0B
   cbr r16, (1<<UDRIE@0)                        ; disable TX data register empty interrupt
   sts UCSR@0B, r16
-  rjmp l_end_%
-l_send_%:
-  sts UDR@0, r16
-  clr r16
-  std Y+UART_HW_IFACE_OFFS_WRITETIMER, r16     ; reset write timer
 l_end_%:
 .endmacro
 ; @end
@@ -200,21 +231,27 @@ l_end_%:
 ; @macro M_UART_HW_Uart_TxCharIsr
 ;
 ; Handler for TXCn interrupt called when a last byte has been completely sent and
-; the data register is empty..
+; the data register is empty.
 ;
 ; @param %0 UART number ("0" for UART0)
 ; @param Y pointer to interface data in SRAM (see @ref UART_HW_IFACE_OFFS_MODE)
-; @clobbers R16, (R17, R18, X)
+; @clobbers R16
 
 .macro M_UART_HW_Uart_TxCharIsr
   ; disable further TXC1 interrupts
   lds r16, UCSR@0B
-  cbr r16, (1<<TXC@0)                           ; disable TXC1 interrupt
+  cbr r16, (1<<TXC@0)                          ; disable TXC1 interrupt
   sts UCSR@0B, r16
-  ; set underrun status (TODO: maybe change this later)
-  ldd r16, Y+UART_HW_IFACE_OFFS_STATUS         ; set underrun error
-  ori r16, (1<<UART_HW_STATUS_UNDERRUN_BIT)
-  std Y+UART_HW_IFACE_OFFS_STATUS, r16
+
+  ; check write mode
+  ldd r16, Y+UART_HW_IFACE_OFFS_WRITEMODE
+  cpi r16, UART_HW_WRITEMODE_WAITBUFFEREMPTY
+  brne l_end_%
+
+  ; change write mode to WRITEBUFFEREMPTY
+  ldi r16, UART_HW_WRITEMODE_WRITEBUFFEREMPTY
+  std Y+UART_HW_IFACE_OFFS_WRITEMODE, r16
+l_end_%:
 .endmacro
 ; @end