From 343562f6ca9c08bfe1e9632e9e27580ad8a92fa4 Mon Sep 17 00:00:00 2001
From: Martin Preuss <martin@aquamaniac.de>
Date: Mon, 29 Jun 2026 17:42:40 +0200
Subject: [PATCH] avr: added hw code for ATtiny 861.

---
 avr/devices/all/0BUILD       |   1 +
 avr/devices/all/hw_tn861.asm | 139 +++++++++++++++++++++++++++++++++++
 2 files changed, 140 insertions(+)
 create mode 100644 avr/devices/all/hw_tn861.asm

diff --git a/avr/devices/all/0BUILD b/avr/devices/all/0BUILD
index 72eda573..33b3b872 100644
--- a/avr/devices/all/0BUILD
+++ b/avr/devices/all/0BUILD
@@ -9,6 +9,7 @@
     hw_tn84.asm
     hw_tn85.asm
     hw_tn841.asm
+    hw_tn861.asm
     hw_m8515.asm
     includes.asm
     main.asm
diff --git a/avr/devices/all/hw_tn861.asm b/avr/devices/all/hw_tn861.asm
new file mode 100644
index 00000000..e6cea14c
--- /dev/null
+++ b/avr/devices/all/hw_tn861.asm
@@ -0,0 +1,139 @@
+; ***************************************************************************
+; copyright   : (C) 2026 by Martin Preuss
+; email       : martin@libchipcard.de
+;
+; ***************************************************************************
+; * This file is part of the project "AqHome".                              *
+; * Please see toplevel file COPYING of that project for license details.   *
+; ***************************************************************************
+
+; Hardware routine  for AtTiny 861 devices
+
+
+.cseg
+
+
+; ---------------------------------------------------------------------------
+; @routine systemInitHardware
+;
+
+systemInitHardware:
+  ; set all ports as inputs and enable internal pull-up resistors
+  ldi r16, 0xff
+  clr r17
+.ifdef PORTA
+  out DDRA, r17  ; all input
+  out PORTA, r16 ; enable pull-up on all
+.endif
+
+.ifdef PORTB
+  out DDRB, r17  ; all input
+  out PORTB, r16 ; enable pull-up on all
+.endif
+
+.ifdef PORTC
+  out DDRC, r17  ; all input
+  out PORTC, r16 ; enable pull-up on all
+.endif
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine systemSetSpeed
+;
+
+systemSetSpeed:
+.if clock == 8000000
+  ldi r16, (1<<CLKPCE)
+  ldi r17, 0
+  out CLKPR, r16
+  out CLKPR, r17
+.endif
+
+.if clock == 1000000
+  ldi r16, (1<<CLKPCE)
+  ldi r17, (1<<CLKPS1) | (1<<CLKPS0)
+  out CLKPR, r16
+  out CLKPR, r17
+.endif
+
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine systemSleep
+;
+
+systemSleep:
+  ; only modify SE, SM1 and SM0
+  cli
+  in r16, MCUCR
+  cbr r16, (1<<SE) | (1<<SM1) | (1<<SM0)
+  out MCUCR, r16
+  sbr r16, (1<<SE) | (0<<SM1) | (0<<SM0)  ; sleep mode "idle", enable
+  out MCUCR, r16
+  sei                        ; make sure interrupts really are enabled
+  sleep                      ; sleep, wait for interrupt
+  cbr r16, (1<<SE) | (1<<SM1) | (1<<SM0)
+  out MCUCR, r16
+  ret
+; @end
+
+
+
+
+; ---------------------------------------------------------------------------
+; @routine systemSetupTimer0
+;
+
+systemSetupTimer0:            ; setup timer for IRQ every 100ms
+  ldi r16, (1<<CS02) | (0<<CS01) | (1<<CS00)  ; Prescaler 1024
+  out TCCR0B, r16
+  
+  ldi r16, (0<<ICEN0) | (0<<TCW0) | (1<<WGM00) ; CTC mode
+  out TCCR0A, r16
+
+; Settings for clock 1Mhz (default)
+; use timer0 with OCR0A=98-1 (irq every 97.65625 millisecs), baseTimerModuleReloadValue 1
+;
+.if clock == 1000000
+  ; CMP-A interrupt about every 100ms
+  ldi r16, 98-1      ; (1,000,000/1024)/10 = 97.65625
+  out OCR0A, r16
+
+  ldi r16, 1
+  sts baseTimerModuleReloadValue, r16
+  sts baseTimerModuleTickCounter, r16
+.endif
+
+;
+; Settings for clock 8Mhz
+; use timer0 with OCR0A=78 (irq every 9.984 millisecs), baseTimerModuleReloadValue 10
+;
+.if clock == 8000000
+  ; CMP-A interrupt about every 10ms
+  ldi r16, 78-1
+  out OCR0A, r16
+
+  ldi r16, 10
+  sts baseTimerModuleReloadValue, r16
+  sts baseTimerModuleTickCounter, r16
+.endif
+
+
+  ldi r16, (1<<OCF0A)             ; clear pending interrupts
+  out TIFR, r16
+  
+  ldi r16, (1<<OCIE0A)            ; Timer/Counter0 Output Compare Match A Interrupt Enable
+  out TIMSK, r16
+ 
+  sec
+  ret
+; @end
+
+
+