From 102f4e65e3807788b65765a6d01ac85cc8f89d63 Mon Sep 17 00:00:00 2001 From: Martin Preuss Date: Mon, 17 Nov 2025 23:02:19 +0100 Subject: [PATCH] added c03. --- avr/devices/0BUILD | 1 + avr/devices/c03/.gitignore | 2 + avr/devices/c03/0BUILD | 18 ++ avr/devices/c03/README | 10 + avr/devices/c03/boot/0BUILD | 32 +++ avr/devices/c03/boot/boot.asm | 159 ++++++++++++++ avr/devices/c03/defs.asm | 195 +++++++++++++++++ avr/devices/c03/main/0BUILD | 34 +++ avr/devices/c03/main/data.asm | 14 ++ avr/devices/c03/main/dlg_netstats.asm | 287 +++++++++++++++++++++++++ avr/devices/c03/main/main.asm | 294 ++++++++++++++++++++++++++ avr/devices/c03/main/win_netstats.asm | 187 ++++++++++++++++ devices/nodes/0BUILD | 1 + devices/nodes/aqua_c03.xml | 12 ++ flashnode.sh | 7 + 15 files changed, 1253 insertions(+) create mode 100644 avr/devices/c03/.gitignore create mode 100644 avr/devices/c03/0BUILD create mode 100644 avr/devices/c03/README create mode 100644 avr/devices/c03/boot/0BUILD create mode 100644 avr/devices/c03/boot/boot.asm create mode 100644 avr/devices/c03/defs.asm create mode 100644 avr/devices/c03/main/0BUILD create mode 100644 avr/devices/c03/main/data.asm create mode 100644 avr/devices/c03/main/dlg_netstats.asm create mode 100644 avr/devices/c03/main/main.asm create mode 100644 avr/devices/c03/main/win_netstats.asm create mode 100644 devices/nodes/aqua_c03.xml diff --git a/avr/devices/0BUILD b/avr/devices/0BUILD index 6350105..8e3d7f9 100644 --- a/avr/devices/0BUILD +++ b/avr/devices/0BUILD @@ -26,6 +26,7 @@ all c01 c02 + c03 n14 n16 n21 diff --git a/avr/devices/c03/.gitignore b/avr/devices/c03/.gitignore new file mode 100644 index 0000000..8e0618c --- /dev/null +++ b/avr/devices/c03/.gitignore @@ -0,0 +1,2 @@ +*.eep.hex +*.obj diff --git a/avr/devices/c03/0BUILD b/avr/devices/c03/0BUILD new file mode 100644 index 0000000..dc4c439 --- /dev/null +++ b/avr/devices/c03/0BUILD @@ -0,0 +1,18 @@ + + + + + + boot + main + + + + defs.asm + README + + + + + + diff --git a/avr/devices/c03/README b/avr/devices/c03/README new file mode 100644 index 0000000..53dfeb9 --- /dev/null +++ b/avr/devices/c03/README @@ -0,0 +1,10 @@ + +C01 +=== + +- Role: Controller with Display +- MCU: AtMega 644P +- Connection: RJ45 +- Periphery: + - Display with SPI + diff --git a/avr/devices/c03/boot/0BUILD b/avr/devices/c03/boot/0BUILD new file mode 100644 index 0000000..ce518c7 --- /dev/null +++ b/avr/devices/c03/boot/0BUILD @@ -0,0 +1,32 @@ + + + + + + + + -I $(builddir) + -I $(srcdir) + -I $(topsrcdir)/avr + -I $(topbuilddir)/avr + + + + + boot.asm + + + + + + + + + + + + + + + + diff --git a/avr/devices/c03/boot/boot.asm b/avr/devices/c03/boot/boot.asm new file mode 100644 index 0000000..9b5bfb4 --- /dev/null +++ b/avr/devices/c03/boot/boot.asm @@ -0,0 +1,159 @@ +; *************************************************************************** +; Source file for base system node on AtMega 644P +; +; This is for the maintenance system (i.e. the flash loader). +; +; All definitions and changes should go into this file. +; *************************************************************************** + +.equ clock=8000000 ; Define the clock frequency + +.nolist +.include "include/m644Pdef.inc" ; Define device ATmega8515 +.list + +.include "../defs.asm" +.include "devices/all/defs.asm" + +.include "common/calls.asm" +.include "common/utils_wait.asm" +.include "common/utils_io.asm" + + + +; *************************************************************************** +; defines + +; --------------------------------------------------------------------------- +; generic + + +.equ NET_BUFFERS_NUM = 6 +.equ NET_BUFFERS_SIZE = 32 + + + +; --------------------------------------------------------------------------- +; firmware settings + +.equ FIRMWARE_VERSION_MAJOR = 0 +.equ FIRMWARE_VERSION_MINOR = 0 +.equ FIRMWARE_VERSION_PATCHLEVEL = 1 + + + +; --------------------------------------------------------------------------- +; LED + +.equ LED_DDR = DDRB +.equ LED_PORT = PORTB +.equ LED_PIN = PINB +.equ LED_PINNUM = PORTB0 + + + + + +; *************************************************************************** +; code segment + +.cseg +.org 0x0000 + + + +; --------------------------------------------------------------------------- +; Reset and interrupt vectors + jmp main ; 1: Reset vector RESET + jmp irqNotSet ; 2: INT0 External Interrupt Request 0 + jmp irqNotSet ; 3: INT1 External Interrupt Request 1 + jmp irqNotSet ; 4: INT2 External Interrupt Request 2 + jmp irqNotSet ; 5: PCINT0 Pin Change Interrupt Request 0 + jmp irqNotSet ; 6: PCINT1 Pin Change Interrupt Request 1 + jmp irqNotSet ; 7: PCINT2 Pin Change Interrupt Request 2 + jmp irqNotSet ; 8: PCINT3 Pin Change Interrupt Request 3 + jmp irqNotSet ; 9: WDT Watchdog Time-out Interrupt + jmp irqNotSet ; 10: TIMER2_COMPA Timer/Counter2 Compare Match A + jmp irqNotSet ; 11: TIMER2_COMPB Timer/Counter2 Compare Match B + jmp irqNotSet ; 12: TIMER2_OVF Timer/Counter2 Overflow + jmp irqNotSet ; 13: TIMER1_CAPT Timer/Counter1 Capture Event + jmp irqNotSet ; 14: TIMER1_COMPA Timer/Counter1 Compare Match A + jmp irqNotSet ; 15: TIMER1_COMPB Timer/Counter1 Compare Match B + jmp irqNotSet ; 16: TIMER1_OVF Timer/Counter1 Overflow + jmp irqNotSet ; 17: TIMER0_COMPA Timer/Counter0 Compare Match A + jmp irqNotSet ; 18: TIMER0_COMPB Timer/Counter0 Compare Match B + jmp irqNotSet ; 19: TIMER0_OVF Timer/Counter0 Overflow + jmp irqNotSet ; 20: SPI_STC Serial Transfer Complete + jmp irqNotSet ; 21: USART0_RXC USART0 Rx Complete + jmp irqNotSet ; 22: USART0_UDRE USART0 Data Register Empty + jmp irqNotSet ; 23: USART0_TXC USART0 Tx Complete + jmp irqNotSet ; 24: ANA_COMP Analog Comparator + jmp irqNotSet ; 25: ADC ADC Conversion Complete + jmp irqNotSet ; 26: EE_RDY EEPROM Ready + jmp irqNotSet ; 27: TWI 2-Wire Interface + jmp irqNotSet ; 28: SPM_RDY Store Program Memory Ready + + + +; --------------------------------------------------------------------------- +; Device Info Block + +devInfoBlock: ; 12 bytes +devInfoManufacturer: .db 'A', 'Q', 'U', 'A' +devInfoId: .db DEVICEINFO_ID, 0 +devInfoVersion: .db DEVICEINFO_VERSION, DEVICEINFO_REVISION ; version, revision +firmwareVersion: .db FIRMWARE_VARIANT_BOOT, FIRMWARE_VERSION_MAJOR + .db FIRMWARE_VERSION_MINOR, FIRMWARE_VERSION_PATCHLEVEL + +firmwareStart: + jmp main ; will be overwritten when flashing + +irqNotSet: + reti + + + +; *************************************************************************** +; main code + + +.org BOOTLOADER_ADDR + + +main: +; ldi r16, 0xb0 ; orig: a0 +; out OSCCAL, r16 + jmp bootLoader ; this routine is in modules/bootloader/main.asm + + + +; *************************************************************************** +; includes + +.include "common/wait_10us.asm" +.include "common/utils_copy_from_flash.asm" +.include "common/utils_copy_sdram.asm" + +.include "modules/flash/defs.asm" +.include "modules/flash/eeprom.asm" +.include "modules/flash/io.asm" +.include "modules/flash/io_com2w.asm" +.include "modules/flash/flash1pmega.asm" +.include "modules/flash/flashxp.asm" +.include "modules/flash/flashprocess.asm" +.include "modules/flash/wait.asm" +.include "modules/bootloader/main.asm" +.include "modules/network/msg/defs.asm" +.include "modules/network/msg/crc.asm" + +;.include "common/debug.asm" + + + +systemSetSpeed: + ; speed not changeable at runtime on this device + ret + + + + diff --git a/avr/devices/c03/defs.asm b/avr/devices/c03/defs.asm new file mode 100644 index 0000000..d18e0ae --- /dev/null +++ b/avr/devices/c03/defs.asm @@ -0,0 +1,195 @@ +; *************************************************************************** +; copyright : (C) 2025 by Martin Preuss +; email : martin@libchipcard.de +; +; *************************************************************************** +; * This file is part of the project "AqHome". * +; * Please see toplevel file COPYING of that project for license details. * +; *************************************************************************** + + +; *************************************************************************** +; +; AtMega644 +; -------- +; LED PB0 1 40 PA0 DEV0 +; DC PB1 2 39 PA1 DEV1 +; INT2 PB2 3 38 PA2 DEV2 +; DSPRES PB3 4 37 PA3 PA3 +; SS PB4 5 36 PA4 PA4 +; MOSI PB5 6 35 PA5 +; MISO PB6 7 34 PA6 +; SCK PB7 8 33 PA7 +; /RESET 9 32 AREF +; VCC 10 31 GND +; GND 11 30 AVCC +; XTAL2 12 29 PC7 +; XTAL1 13 28 PC6 +; RXD PD0 14 27 PC5 +; TXD PD1 15 26 PC4 +; PD2 16 25 PC3 +; INT1 PD3 17 24 PC2 +; AUX_PD4 PD4 18 23 PC1 +; DSPLED PD5 19 22 PC0 +; PD6 20 21 PD7 +; -------- +; +; *************************************************************************** + + + +.equ BOOTLOADER_ADDR = 0x7c00 + +.equ FIRMWARE_VARIANT_BOOT = 0 +.equ FIRMWARE_VARIANT_TEMP_WINDOW = 1 + +.equ DEVICEINFO_ID = 'C' +.equ DEVICEINFO_VERSION = 3 +.equ DEVICEINFO_REVISION = 0 + + + +; --------------------------------------------------------------------------- +; LED module + +.equ LED_SIMPLE_ONTIME = 1 ; shorter +.equ LED_SIMPLE_OFFTIME = 50 ; longer +.equ LED_SIMPLE_DDR = DDRB +.equ LED_SIMPLE_PORT = PORTB +.equ LED_SIMPLE_PORTIN = PINB +.equ LED_SIMPLE_PINNUM = PORTB0 + + + +; --------------------------------------------------------------------------- +; COM module + +.equ COM_BIT_LENGTH = 52000 ; 104000ns=9600, 52000ns=19200, 26000ns=38400 +.equ COM_HALFBIT_LENGTH = 26000 ; see https://de.wikipedia.org/wiki/Universal_Asynchronous_Receiver_Transmitter + +.equ COM_DATA_DDR = DDRA +.equ COM_DATA_INPUT = PINA +.equ COM_DATA_OUTPUT = PORTA +.equ COM_DATA_PIN = PORTA6 + +.equ COM_CLK_DDR = DDRA +.equ COM_CLK_INPUT = PINA +.equ COM_CLK_OUTPUT = PORTA +.equ COM_CLK_PIN = PORTA7 + +; pin change interrupt register and bit +.equ COM_IRQ_ADDR_CLK = PCMSK0 +.equ COM_IRQ_BIT_CLK = PCINT7 ; PA7 + +; interrupt control register +.equ COM_IRQ_ICR_ADDR = PCICR ; PCICR on AtMega644P, GIMSK on AtTiny +.equ COM_IRQ_ICR_BIT = PCIE0 + +; interrupt flag/mask register +.equ COM_IRQ_IFR_ADDR = PCIFR ; PCIFR on AtMega644P, GIFR on AtTiny +.equ COM_IRQ_IFR_BIT = PCIF0 + +.equ COM_IRQ_GIFR_CLK = INTF0 +;.equ COM_IRQ_GIMSK_CLK = PCIE0 + + + +; --------------------------------------------------------------------------- +; SPI hardware module + +.equ SPIHW_SS_DDR = DDRB +.equ SPIHW_SS_INPUT = PINB +.equ SPIHW_SS_OUTPUT = PORTB +.equ SPIHW_SS_PIN = PORTB4 + +.equ SPIHW_MOSI_DDR = DDRB +.equ SPIHW_MOSI_INPUT = PINB +.equ SPIHW_MOSI_OUTPUT = PORTB +.equ SPIHW_MOSI_PIN = PORTB5 + +.equ SPIHW_MISO_DDR = DDRB +.equ SPIHW_MISO_INPUT = PINB +.equ SPIHW_MISO_OUTPUT = PORTB +.equ SPIHW_MISO_PIN = PORTB6 + +.equ SPIHW_SCK_DDR = DDRB +.equ SPIHW_SCK_INPUT = PINB +.equ SPIHW_SCK_OUTPUT = PORTB +.equ SPIHW_SCK_PIN = PORTB7 + +.equ SPIHW_SS0_DDR = DDRA +.equ SPIHW_SS0_OUTPUT = PORTA +.equ SPIHW_SS0_INPUT = PORTA +.equ SPIHW_SS0_PIN = PORTA0 + +.equ SPIHW_SS1_DDR = DDRA +.equ SPIHW_SS1_OUTPUT = PORTA +.equ SPIHW_SS1_INPUT = PORTA +.equ SPIHW_SS1_PIN = PORTA1 + +.equ SPIHW_SS2_DDR = DDRA +.equ SPIHW_SS2_OUTPUT = PORTA +.equ SPIHW_SS2_INPUT = PORTA +.equ SPIHW_SS2_PIN = PORTA2 + + + +; --------------------------------------------------------------------------- +; ILI9341 module + +.equ DISPLAY_WIDTH = 320 +.equ DISPLAY_HEIGHT = 240 + +.equ ILI9341_DEVICENUM = 0 +.equ ILI9341_DSP_WIDTH = DISPLAY_WIDTH +.equ ILI9341_DSP_HEIGHT = DISPLAY_HEIGHT + +.equ ILI9341_RESET_DDR = DDRB +.equ ILI9341_RESET_OUTPUT = PORTB +.equ ILI9341_RESET_INPUT = PORTB +.equ ILI9341_RESET_PIN = PORTB3 + +.equ ILI9341_DC_DDR = DDRB +.equ ILI9341_DC_OUTPUT = PORTB +.equ ILI9341_DC_INPUT = PORTB +.equ ILI9341_DC_PIN = PORTB1 + +.equ ILI9341_LED_DDR = DDRD +.equ ILI9341_LED_OUTPUT = PORTD +.equ ILI9341_LED_INPUT = PORTD +.equ ILI9341_LED_PIN = PORTD5 + + + +; --------------------------------------------------------------------------- +; XPT2046 module + +.equ XPT2046_DEVICENUM = 1 + + + +; --------------------------------------------------------------------------- +; ComOnUart module + +;.equ USART0_DATAREG = UDR +;.equ UCSR0A = UCSRA +;.equ UCSR0B = UCSRB +;.equ UCSR0C = UCSRC +;.equ UBRR0L = UBRRL +;.equ UBRR0H = UBRRH + +;.equ UCSZ00 = UCSZ0 +;.equ UCSZ01 = UCSZ1 +;.equ UDRE0 = UDRE +;.equ RXC0 = RXC +;.equ TXC0 = TXC +;.equ FE0 = FE +;.equ DOR0 = DOR +;.equ UPE0 = UPE +;.equ RXEN0 = RXEN +;.equ TXEN0 = TXEN +;.equ USBS0 = USBS +;.equ RXCIE0 = RXCIE +;.equ UDRIE0 = UDRIE + + diff --git a/avr/devices/c03/main/0BUILD b/avr/devices/c03/main/0BUILD new file mode 100644 index 0000000..725937d --- /dev/null +++ b/avr/devices/c03/main/0BUILD @@ -0,0 +1,34 @@ + + + + + + + + -I $(builddir) + -I $(srcdir) + -I $(topsrcdir)/avr + -I $(topbuilddir)/avr + + + + + main.asm + + + + + + + + + + + + data.asm + + + + + + diff --git a/avr/devices/c03/main/data.asm b/avr/devices/c03/main/data.asm new file mode 100644 index 0000000..31ccc2f --- /dev/null +++ b/avr/devices/c03/main/data.asm @@ -0,0 +1,14 @@ +; *************************************************************************** +; copyright : (C) 2025 by Martin Preuss +; email : martin@libchipcard.de +; +; *************************************************************************** +; * This file is part of the project "AqHome". * +; * Please see toplevel file COPYING of that project for license details. * +; *************************************************************************** + + + +.dseg + + diff --git a/avr/devices/c03/main/dlg_netstats.asm b/avr/devices/c03/main/dlg_netstats.asm new file mode 100644 index 0000000..4c294dc --- /dev/null +++ b/avr/devices/c03/main/dlg_netstats.asm @@ -0,0 +1,287 @@ +; *************************************************************************** +; copyright : (C) 2025 by Martin Preuss +; email : martin@libchipcard.de +; +; *************************************************************************** +; * This file is part of the project "AqHome". * +; * Please see toplevel file COPYING of that project for license details. * +; *************************************************************************** + +#ifndef AQH_AVR_DEVICE_C03_DLG_NETSTATS_ASM +#define AQH_AVR_DEVICE_C03_DLG_NETSTATS_ASM + +.equ DLG_NETSTATS_TIMER_100ms = 50 + +.equ DLG_NETSTATS_FLAGS_BUTTON_DOWN_BIT = 0 + + +.cseg + + + +DlgNetStats_Init: + ldi yl, LOW(dlgNetstats) + ldi yh, HIGH(dlgNetstats) + bigcall Dialog_Init + ; set handler + ldi r16, LOW(DlgNetStats_Handler) + std Y+DIALOG_OFFS_HANDLER_LO, r16 + ldi r16, HIGH(DlgNetStats_Handler) + std Y+DIALOG_OFFS_HANDLER_HI, r16 + + ; clear vars + clr r16 + sts dlgNetstatsUpdateNum, r16 + sts dlgNetstatsUpdateNum+1, r16 + sts dlgNetstatsTimer, r16 + sts dlgNetstatsFlags, r16 + + ret +; @end + + + +DlgNetStats_Handler: + cpi r23, (DIALOG_FN_TIMER+1) + brcc DlgNetStats_Handler_ret + ldi zl, LOW(DlgNetStats_Handler_Fns) + ldi zh, HIGH(DlgNetStats_Handler_Fns) + add zl, r23 + adc zh, r23 + sub zh, r23 + ijmp +DlgNetStats_Handler_ret: + ret +; @end + + + +DlgNetStats_Handler_Fns: + rjmp dlgNetStatsOnInit + rjmp dlgNetStatsOnFini + rjmp dlgNetStatsOnShow + rjmp dlgNetStatsOnHide + ret ; rjmp dlgNetStatsOnTouch + rjmp dlgNetStatsOnTimer + + + +dlgNetStatsOnInit: + ret + + + +dlgNetStatsOnFini: + ret + + + +dlgNetStatsOnShow: + push yl + push yh + mov yl, xl + mov yh, xh + rcall DlgNetStats_Show + pop yh + pop yl + ret + + + +dlgNetStatsOnHide: + ret + + + +dlgNetStatsOnTouch: + mov r16, r18 + mov r17, r18 + mov yl, xl + mov yh, xh + + ; check for press change event + andi r17, (1< aqua_c01.xml aqua_c02.xml + aqua_c03.xml aqua_n06.xml aqua_n11.xml aqua_n12.xml diff --git a/devices/nodes/aqua_c03.xml b/devices/nodes/aqua_c03.xml new file mode 100644 index 0000000..11bed37 --- /dev/null +++ b/devices/nodes/aqua_c03.xml @@ -0,0 +1,12 @@ + + + AQUA + C + 3 + + + + + + + diff --git a/flashnode.sh b/flashnode.sh index 2b9adf8..c04a68c 100755 --- a/flashnode.sh +++ b/flashnode.sh @@ -23,6 +23,13 @@ case $NODE in EFUSE_ARG="-U efuse:w:0xFF:m" FILE_ARG="-U flash:w:./0-build/avr/devices/c02/boot/c02_boot.hex" ;; + c03) + DEVICE_ARG="-p m644p" + HFUSE_ARG="-U hfuse:w:0xD5:m" + LFUSE_ARG="-U lfuse:w:0xE2:m" + EFUSE_ARG="-U efuse:w:0xFF:m" + FILE_ARG="-U flash:w:./0-build/avr/devices/c03/boot/c03_boot.hex" + ;; n14) DEVICE_ARG="-p t85" HFUSE_ARG="-U hfuse:w:0xD7:m"