split uart_bitbang2 into multiple files.

avr/modules/uart_bitbang2/msglevel.asm

@@ -0,0 +1,175 @@
+; ***************************************************************************
+; copyright   : (C) 2025 by Martin Preuss
+; email       : martin@libchipcard.de
+;
+; ***************************************************************************
+; * This file is part of the project "AqHome".                              *
+; * Please see toplevel file COPYING of that project for license details.   *
+; ***************************************************************************
+
+
+
+; ***************************************************************************
+; code
+
+
+
+; ---------------------------------------------------------------------------
+; @routine uartBitbang_ReceiveAndCheckMsg
+;
+; Receive a packet into buffer pointed to by X.
+; Expects interrupts to be disabled.
+;
+; @param R18 COM address to listen to
+; @param R19 max buffer size
+; @param X   buffer to receive to
+; @return CFLAG set if msg received, cleared on error
+; @clobbers R16, R19 (R17, R20, R21, R22, R24, R25)
+
+uartBitbang_ReceiveAndCheckMsg:
+  push xl
+    push xh
+      rcall uartBitbang_RawReceiveMsg        ; (R16, R17, R19, R20, R21, R22, R24, R25, X)
+    pop xh
+  pop xl
+  brcs uartBitbang_ReceiveAndCheckMsg_recvd
+  ; fall-through, return with CF cleared (from uartBitbang_RawReceiveMsg)
+  ret
+uartBitbang_ReceiveAndCheckMsg_recvd:
+  push xl
+    push xh
+      rcall NETMSG_CheckMessageInBuffer      ; (R16, R17, R18, R19, R20, X)
+    pop xh
+  pop xl
+  brcs uartBitbang_ReceiveAndCheckMsg_msgOk
+  ldi r16, NET_IFACE_OFFS_ERR_CONTENT_LOW
+  rcall NET_Interface_IncCounter16          ; (R24, R25)
+  clc
+  ret
+uartBitbang_ReceiveAndCheckMsg_msgOk:
+  ldi r16, NET_IFACE_OFFS_PACKETSIN_LOW
+  rcall NET_Interface_IncCounter16          ; (R24, R25)
+  sec
+  ret
+; @end
+
+
+
+; ---------------------------------------------------------------------------
+; @routine uartBitbang_RawReceiveMsg
+;
+; Receive a packet into buffer pointed to by X.
+; Expects interrupts to be disabled.
+;
+; @param R18 COM address to listen to
+; @param R19 max buffer size
+; @param X   buffer to receive to
+; @return CFLAG set if msg received, cleared on error (see R16)
+; @return R16   if CFLAG cleared: 0=message not for this node, otherwise error
+; @clobbers R16, R19 (R17, R20, R21, R22, R24, R25, X)
+
+uartBitbang_RawReceiveMsg:
+  cpi r19, 3
+  brcs uartBitbang_RawReceiveMsg_eBadSize
+  ; read destination address
+  rcall uartBitbang_ReceiveByte             ; read byte (R16, R17, R20, R21, R22)
+  brcc uartBitbang_RawReceiveMsg_eIo
+  cp r16, r18
+  breq uartBitbang_RawReceiveMsg_forMe
+  cpi r16, 0xff
+  breq uartBitbang_RawReceiveMsg_forMe
+  clr r16
+  rjmp uartBitbang_RawReceiveMsg_clcRet
+uartBitbang_RawReceiveMsg_forMe:
+  subi r19, 1
+  brcs uartBitbang_RawReceiveMsg_eBadSize
+  st X+, r16
+  ; read size of msg payload (e.g. number of msg bytes following minus CRC byte)
+  rcall uartBitbang_ReceiveByte             ; read byte (R16, R17, R20, R21, R22)
+  brcc uartBitbang_RawReceiveMsg_eIo
+  inc r16                                   ; account for crc byte
+  subi r19, 1
+  brcs uartBitbang_RawReceiveMsg_eBadSize
+  st X+, r16                                ; store msg payload size
+  sub r19, r16                              ; check msg size against remaining buffer size
+  brcs uartBitbang_RawReceiveMsg_eBadSize
+  mov r19, r16
+uartBitbang_RawReceiveMsg_loop:
+    rcall uartBitbang_ReceiveByte           ; read byte (R16, R17, R20, R21, R22)
+    brcc uartBitbang_RawReceiveMsg_eIo
+    st X+, r16                              ; store msg
+    dec r19
+  brne uartBitbang_RawReceiveMsg_loop
+  sec
+  rjmp uartBitbang_RawReceiveMsg_end
+uartBitbang_RawReceiveMsg_eBadSize:
+  ldi r16, NET_IFACE_OFFS_ERR_MSGSIZE_LOW
+  rjmp uartBitbang_RawReceiveMsg_incCounterRet
+uartBitbang_RawReceiveMsg_eIo:
+  ldi r16, NET_IFACE_OFFS_ERR_IO_LOW
+uartBitbang_RawReceiveMsg_incCounterRet:
+  rcall NET_Interface_IncCounter16          ; (R24, R25)
+uartBitbang_RawReceiveMsg_clcRet:
+  clc
+uartBitbang_RawReceiveMsg_end:
+  ret
+; @end
+
+
+
+
+
+
+; ---------------------------------------------------------------------------
+; @routine uartBitbang_SendMsg
+;
+; Send packet over wire, handle ATTN line.
+;
+; @param  X ptr to buffer to send
+; @return CFLAGS set if okay, cleared otherwise (index of error variable in R16)
+; @return R16 index of error variable (if CFLAGS cleared)
+; @clobbers R16, R22 (R17, R21, X)
+
+uartBitbang_SendMsg:
+  rcall uartBitbang_AcquireBus
+  brcc uartBitbang_SendMsg_lineBusyError
+  
+  rcall uartBitbang_WaitForOneBitLength          ; wait for one bit duration (R22)
+  rcall uartBitbang_WaitForOneBitLength          ; wait for one bit duration (R22)
+  rcall uartBitbang_WaitForOneBitLength          ; wait for one bit duration (R22)
+
+  adiw xh:xl, NETMSG_OFFS_MSGLEN
+  ld r17, X
+  sbiw xh:xl, NETMSG_OFFS_MSGLEN
+  inc r17                                        ; account for dest addr
+  inc r17                                        ; account for msglen byte
+  inc r17                                        ; account for crc byte
+
+uartBitbang_SendMsg_loop:
+    rcall uartBitbang_WaitForOneBitLength        ; wait for one bit duration (R22)
+
+    ld r16, X+
+    rcall uartBitbang_SendByte                   ; send byte (R16, R21, R22)
+    brcc uartBitbang_SendMsg_releaseBusRet
+    dec r17
+  brne uartBitbang_SendMsg_loop
+  sec
+uartBitbang_SendMsg_releaseBusRet:
+  cbi COM_ATTN_DDR, COM_ATTN_PIN                 ; release ATTN line (by setting direction to IN)
+  brcc uartBitbang_SendMsg_ioError
+  ; packet successfully sent
+  ret
+uartBitbang_SendMsg_ioError:
+  ldi r16, NET_IFACE_OFFS_ERR_COLLISIONS_LOW
+  ret
+uartBitbang_SendMsg_lineBusyError:
+  ldi r16, NET_IFACE_OFFS_ERR_BUSY_LOW
+  ret
+; @end
+
+
+
+
+
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