avr: more work on t03 and hw uart modules.
Too complicated, will start new...
This commit is contained in:
@@ -24,6 +24,8 @@
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;.equ clock=1000000 ; Define the clock frequency
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;.equ clock=1000000 ; Define the clock frequency
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.equ clock=8000000 ; Define the clock frequency
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.equ clock=8000000 ; Define the clock frequency
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; .equ SEND_DEVICE_EVERY = 3000
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.equ SEND_DEVICE_EVERY = 100 ; every 10s
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.nolist
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.nolist
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@@ -86,7 +88,7 @@
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; ---------------------------------------------------------------------------
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; ---------------------------------------------------------------------------
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; Reset and interrupt vectors (will be removed as soon as we can flash data over COM)
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; Reset and interrupt vectors
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rjmp BOOTLOADER_ADDR ; 1: RESET Reset vector use this for flashed system
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rjmp BOOTLOADER_ADDR ; 1: RESET Reset vector use this for flashed system
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reti ; 2: INT0 External Interrupt Request 0
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reti ; 2: INT0 External Interrupt Request 0
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@@ -114,9 +116,9 @@
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reti ; 24: USART0_DRE USART0 Data Register Empty
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reti ; 24: USART0_DRE USART0 Data Register Empty
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reti ; 25: USART0_TXC USART0 Tx Complete
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reti ; 25: USART0_TXC USART0 Tx Complete
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reti ; 26: USART1_RXS USART1 Rx Start
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reti ; 26: USART1_RXS USART1 Rx Start
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reti ; 27: USART1_RXC USART1 Rx Complete
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rjmp TtyOnUart1_RxCharIsr ; 27: USART1_RXC USART1 Rx Complete
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reti ; 28: USART1_DRE USART1 Data Register Empty
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rjmp TtyOnUart1_TxUdreIsr ; 28: USART1_DRE USART1 Data Register Empty
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reti ; 29: USART1_TXC USART1 Tx Complete
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rjmp TtyOnUart1_TxCharIsr ; 29: USART1_TXC USART1 Tx Complete
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reti ; 30: TWI Two-Wire-Interface
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reti ; 30: TWI Two-Wire-Interface
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reti ; 31: RESERVED reserved
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reti ; 31: RESERVED reserved
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@@ -145,8 +147,10 @@ firmwareStart:
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rcall initHardware
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rcall initHardware
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; rcall watchdogOff ; turn off watchdog timer (sometimes it stays on after reboot)
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; rcall watchdogOff ; turn off watchdog timer (sometimes it stays on after reboot)
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rcall initModules
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rcall Utils_Init
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rcall Utils_SetupUid
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rcall Utils_SetupUid
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rcall initModules
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sbi LED_SIMPLE_DDR, LED_SIMPLE_PINNUM ; out
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sbi LED_SIMPLE_DDR, LED_SIMPLE_PINNUM ; out
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sbi LED_SIMPLE_PORT, LED_SIMPLE_PINNUM ; off
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sbi LED_SIMPLE_PORT, LED_SIMPLE_PINNUM ; off
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@@ -197,7 +201,7 @@ onSystemTimerTick:
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#ifdef MODULES_LED_SIMPLE
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#ifdef MODULES_LED_SIMPLE
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rcall LedSimple_Every100ms
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rcall LedSimple_Every100ms
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#endif
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#endif
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rcall maybeSendDeviceMsg
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rcall TtyOnUart1_Periodically
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rcall TtyOnUart1_Periodically
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ret
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ret
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@@ -227,11 +231,15 @@ initHardware:
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initModules:
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initModules:
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rcall Utils_Init
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rcall BaseTimer_Init
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rcall BaseTimer_Init
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rcall LedSimple_Init
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rcall LedSimple_Init
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rcall UART_HW_Init
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rcall UART_HW_Init
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rcall TtyOnUart1_Init
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rcall TtyOnUart1_Init
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ldi r16, LOW(SEND_DEVICE_EVERY)
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sts deviceCounter, r16
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ldi r16, HIGH(SEND_DEVICE_EVERY)
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sts deviceCounter+1, r16
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ret
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ret
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; @end
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; @end
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@@ -256,6 +264,7 @@ initModules:
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.include "modules/led_simple/main.asm"
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.include "modules/led_simple/main.asm"
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.include "modules/com2/defs.asm"
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.include "modules/com2/defs.asm"
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.include "modules/com2/crc.asm"
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.include "modules/com2/crc.asm"
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.include "modules/comproto/defs.asm"
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.include "modules/uart_hw/defs.asm"
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.include "modules/uart_hw/defs.asm"
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.include "modules/uart_hw/buffers.asm"
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.include "modules/uart_hw/buffers.asm"
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.include "modules/uart_hw/lowlevel.asm"
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.include "modules/uart_hw/lowlevel.asm"
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@@ -267,6 +276,136 @@ initModules:
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maybeSendDeviceMsg:
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ldi yl, LOW(ttyOnUart1_iface)
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ldi yh, HIGH(ttyOnUart1_iface)
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lds r24, deviceCounter
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lds r25, deviceCounter+1
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sbiw r25:r24, 1
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brne maybeSendDeviceMsg_storeCounter
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; send device msg
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rcall UART_HW_FixedBuffers_Alloc
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brcc maybeSendDeviceMsg_resetCounter
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push r16
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adiw xh:xl, 1
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rcall writeDeviceMsg
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pop r16
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rcall UART_HW_InterfaceAddOutgoingMsgNum
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; reset counter
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maybeSendDeviceMsg_resetCounter:
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ldi r24, LOW(SEND_DEVICE_EVERY)
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ldi r25, HIGH(SEND_DEVICE_EVERY)
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maybeSendDeviceMsg_storeCounter:
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sts deviceCounter, r24
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sts deviceCounter+1, r25
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ret
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writeDeviceMsg:
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ldi r16, 0xff
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st X+, r16 ; dest address
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ldi r16, 18 ; msg code+src address+12 payload bytes
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st X+, r16 ; msg len
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ldi r16, CPRO_CMD_DEVICE
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st X+, r16 ; msg code
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clr r16
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st X+, r16 ; src address
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rcall addUidToBuffer ; (r16, r18, r19, r20, r21)
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ldi zh, HIGH(devInfoBlock*2) ; 6-17: devInfoBlock
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ldi zl, LOW(devInfoBlock*2)
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ldi r18, 12
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rcall Utils_CopyFromFlash ; (R17, R18, X, Y)
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sbiw xh:xl, 20 ; go back to beginning of message (1 byte dst addr, 1 byte length, 18 bytes payload)
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rcall com2CalcAndAddChecksumByte ; (R16, R17, R18, R19, R20, X)
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sbiw xh:xl, 21 ; go back to beginning of message (1 byte dst addr, 1 byte length, 18 bytes payload, 1 byte crc)
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ret
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addUidToBuffer:
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push xh
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push xl
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rcall Utils_ReadUid ; (R16, X)
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pop xl
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pop xh
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st X+, r18
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st X+, r19
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st X+, r20
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st X+, r21
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ret
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DEBUG1:
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ldi r19, 10
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ldi r20, 2
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ldi r21, 8
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rcall blinkLed
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rjmp DEBUG1
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DEBUG2:
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ldi r19, 50
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ldi r20, 1
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ldi r21, 1
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rcall blinkLed
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rjmp DEBUG2
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; @param r19 loop count
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; @param r20 on time
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; @param r21 off time
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; @clobbers (R16, R18, R22, R24, R25)
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blinkLed:
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cbi LED_SIMPLE_PORT, LED_SIMPLE_PINNUM ; on
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mov r22, r20
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rcall waitForMultiple100ms ; (R252
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sbi LED_SIMPLE_PORT, LED_SIMPLE_PINNUM ; off
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mov r22, r21
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rcall waitForMultiple100ms ; (R22)
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dec r19
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brne blinkLed
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ret
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; @param r22 number of 100ms periods to wait
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waitForMultiple100ms:
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waitForMultiple100ms_loop:
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push r22
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rcall waitFor100ms
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pop r22
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dec r22
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brne waitForMultiple100ms_loop
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ret
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waitFor100ms:
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ldi r22, 10
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waitFor100ms_loop:
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push r22
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rcall waitFor10ms
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pop r22
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dec r22
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brne waitFor100ms_loop
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ret
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waitFor10ms:
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ldi r22, 100
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waitFor10ms_loop:
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push r22
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rcall Utils_WaitFor100MicroSecs
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pop r22
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dec r22
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brne waitFor10ms_loop
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ret
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; ***************************************************************************
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; ***************************************************************************
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; data in SRAM
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; data in SRAM
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@@ -275,18 +414,8 @@ initModules:
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programRamBegin:
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programRamBegin:
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; nothing for now
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; nothing for now
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flashUid: .byte 4
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flashUid: .byte 4
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deviceCounter: .byte 2
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programRamEnd:
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programRamEnd:
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; macro test: can we use parameters for names? -> yes, we can ;-)
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.macro m_testMacro
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testname@0:
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rjmp testname@0
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.endm
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macroTest:
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m_testMacro 1
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@@ -26,9 +26,9 @@
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.equ UART_HW_MODE_SKIPPING = 3
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.equ UART_HW_MODE_SKIPPING = 3
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.equ UART_HW_MODE_W_IDLE = 0
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.equ UART_HW_MODE_W_IDLE = 0
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.equ UART_HW_MODE_WRITING = 8
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.equ UART_HW_MODE_WRITING = 16
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.equ UART_HW_MODE_WAITBUFFEREMPTY = 9
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.equ UART_HW_MODE_WAITBUFFEREMPTY = 17
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.equ UART_HW_MODE_WRITEBUFFEREMPTY = 10
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.equ UART_HW_MODE_WRITEBUFFEREMPTY = 18
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.equ UART_HW_STATUS_UNDERRUN_BIT = 0
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.equ UART_HW_STATUS_UNDERRUN_BIT = 0
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@@ -58,25 +58,31 @@ UART_HW_InterfaceInit:
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clr r16
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clr r16
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rcall Utils_FillSram ; (R17, X)
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rcall Utils_FillSram ; (R17, X)
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; reset ringbuffer for recvd chars
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; reset ringbuffer for recvd chars
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m_ringbuffer_y_reset UART_HW_IFACE_READBUF_SIZE, \
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m_ringbuffer_y_reset UART_HW_IFACE_OFFS_READBUF_MAX, \
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UART_HW_IFACE_OFFS_READBUF_USED, \
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UART_HW_IFACE_OFFS_READBUF_USED, \
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UART_HW_IFACE_OFFS_READBUF_RDPOS, \
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UART_HW_IFACE_OFFS_READBUF_RDPOS, \
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UART_HW_IFACE_OFFS_READBUF_WRPOS, \
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UART_HW_IFACE_OFFS_READBUF_WRPOS, \
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UART_HW_IFACE_OFFS_READBUF_DATA
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UART_HW_IFACE_OFFS_READBUF_DATA
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ldi r16, UART_HW_IFACE_READBUF_SIZE
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std Y+UART_HW_IFACE_OFFS_READBUF_MAX, r16
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; reset ringbuffer for chars to transmit
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; reset ringbuffer for chars to transmit
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m_ringbuffer_y_reset UART_HW_IFACE_WRITEBUF_SIZE, \
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m_ringbuffer_y_reset UART_HW_IFACE_OFFS_WRITEBUF_MAX, \
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UART_HW_IFACE_OFFS_WRITEBUF_USED, \
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UART_HW_IFACE_OFFS_WRITEBUF_USED, \
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UART_HW_IFACE_OFFS_WRITEBUF_RDPOS, \
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UART_HW_IFACE_OFFS_WRITEBUF_RDPOS, \
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UART_HW_IFACE_OFFS_WRITEBUF_WRPOS, \
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UART_HW_IFACE_OFFS_WRITEBUF_WRPOS, \
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UART_HW_IFACE_OFFS_WRITEBUF_DATA
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UART_HW_IFACE_OFFS_WRITEBUF_DATA
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ldi r16, UART_HW_IFACE_WRITEBUF_SIZE
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std Y+UART_HW_IFACE_OFFS_WRITEBUF_MAX, r16
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; reset ringbuffer for messages to be sent
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; reset ringbuffer for messages to be sent
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m_ringbuffer_y_reset UART_HW_IFACE_OUTMSGBUF_SIZE, \
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m_ringbuffer_y_reset UART_HW_IFACE_OFFS_OUTMSGBUF_MAX, \
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UART_HW_IFACE_OFFS_OUTMSGBUF_USED, \
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UART_HW_IFACE_OFFS_OUTMSGBUF_USED, \
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UART_HW_IFACE_OFFS_OUTMSGBUF_RDPOS, \
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UART_HW_IFACE_OFFS_OUTMSGBUF_RDPOS, \
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UART_HW_IFACE_OFFS_OUTMSGBUF_WRPOS, \
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UART_HW_IFACE_OFFS_OUTMSGBUF_WRPOS, \
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UART_HW_IFACE_OFFS_OUTMSGBUF_DATA
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UART_HW_IFACE_OFFS_OUTMSGBUF_DATA
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ldi r16, UART_HW_IFACE_OUTMSGBUF_SIZE
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std Y+UART_HW_IFACE_OFFS_OUTMSGBUF_MAX, r16
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ldi r16, 0xff
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ldi r16, 0xff
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std Y+UART_HW_IFACE_OFFS_READMSG_BUFNUM, r16
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std Y+UART_HW_IFACE_OFFS_READMSG_BUFNUM, r16
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@@ -87,13 +87,14 @@ uartHwWriteUptoNumBytes:
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ldd xl, Y+UART_HW_IFACE_OFFS_WRITEMSG_PTR
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ldd xl, Y+UART_HW_IFACE_OFFS_WRITEMSG_PTR
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ldd xh, Y+UART_HW_IFACE_OFFS_WRITEMSG_PTR+1
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ldd xh, Y+UART_HW_IFACE_OFFS_WRITEMSG_PTR+1
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uartHwWriteUptoNumBytes_loop:
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uartHwWriteUptoNumBytes_loop:
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ld r16, X+
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ld r16, X
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push xl
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push xl
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push xh
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push xh
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rcall UART_HW_InterfaceWriteToWriteBuffer ; (R17, R18, X)
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rcall UART_HW_InterfaceWriteToWriteBuffer ; (R17, R18, X)
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pop xh
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pop xh
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pop xl
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pop xl
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brcc uartHwWriteUptoNumBytes_done
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brcc uartHwWriteUptoNumBytes_done
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adiw xh:xl, 1
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inc r21
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inc r21
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dec r20
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dec r20
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brne uartHwWriteUptoNumBytes_loop
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brne uartHwWriteUptoNumBytes_loop
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@@ -1,319 +0,0 @@
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; ***************************************************************************
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; copyright : (C) 2025 by Martin Preuss
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; email : martin@libchipcard.de
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;
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; ***************************************************************************
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; * This file is part of the project "AqHome". *
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; * Please see toplevel file COPYING of that project for license details. *
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; ***************************************************************************
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; ---------------------------------------------------------------------------
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; @routine UART_HW_Uart1_RawInit @global
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;
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; @clobbers R16, R17
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UART_HW_Uart1_RawInit:
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; set baudrate
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.if clock == 8000000
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ldi r16, 25 ; (19.2Kb/s at 8MHz)
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ldi r17, 0
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.endif
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.if clock == 1000000
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ldi r16, 3 ; (19.2Kb/s at 1MHz)
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ldi r17, 0
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.endif
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sts UBRR1H, r17
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sts UBRR1L, r16
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; set character format (asynchronous USART, 8-bit, one stop bit, no parity)
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ldi r16, (3<<UCSZ10)
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sts UCSR1C, r16
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ret
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; @end
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; ---------------------------------------------------------------------------
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; @routine UART_HW_Uart1_RawSendPacket
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; Send packet.
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;
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; @param X buffer to send
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; @return CFLAG: set if okay (packet sent), cleared on error
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; @clobbers r16, r17, X
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UART_HW_Uart1_RawSendPacket:
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adiw xh:xl, 1
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ld r17, X
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sbiw xh:xl, 1
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|
||||||
ldi r16, 3 ; add DEST, LEN, CRC bytes
|
|
||||||
add r17, r16
|
|
||||||
|
|
||||||
lds r16, UCSR1B
|
|
||||||
; cbr r16, (1<<UDRIE1) ; disable DRE interrupt
|
|
||||||
sbr r16, (1<<TXEN1) ; enable transmit
|
|
||||||
sts UCSR1B, r16
|
|
||||||
|
|
||||||
;; clr r16 ; clear all pending interrupts
|
|
||||||
;; sts UCSR1A, r16
|
|
||||||
|
|
||||||
;ldi r17, 20
|
|
||||||
|
|
||||||
UART_HW_Uart1_RawSendPacket_loop:
|
|
||||||
lds r16, UCSR1A
|
|
||||||
sbrs r16, UDRE1
|
|
||||||
rjmp UART_HW_Uart1_RawSendPacket_loop
|
|
||||||
sbr r16, (1<<TXC1)
|
|
||||||
sts UCSR1A, r16
|
|
||||||
ld r16, X+
|
|
||||||
sts UDR1, r16
|
|
||||||
dec r17
|
|
||||||
brne UART_HW_Uart1_RawSendPacket_loop
|
|
||||||
; disable transmit
|
|
||||||
; lds r16, UCSR1B
|
|
||||||
; cbr r16, (1<<TXEN1) ; disable transmit
|
|
||||||
; sts UCSR1B, r16
|
|
||||||
sec
|
|
||||||
ret
|
|
||||||
; @end
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
; ---------------------------------------------------------------------------
|
|
||||||
; @routine UART_HW_Uart1_EnableRawRecv @global
|
|
||||||
;
|
|
||||||
; Enable receiving messages in raw mode.
|
|
||||||
;
|
|
||||||
; @clobbers: r16
|
|
||||||
|
|
||||||
UART_HW_Uart1_EnableRawRecv:
|
|
||||||
lds r16, UCSR1B
|
|
||||||
; cbr r16, (1<<RXCIE1) ; disable RX complete interrupt
|
|
||||||
ori r16, (1<<RXEN1) ; enable receive
|
|
||||||
sts UCSR1B, r16
|
|
||||||
ret
|
|
||||||
; @end
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
; ---------------------------------------------------------------------------
|
|
||||||
; @routine UART_HW_Uart1_DisableRawRecv @global
|
|
||||||
;
|
|
||||||
; Disable receiving messages in raw mode.
|
|
||||||
;
|
|
||||||
; @clobbers: r16
|
|
||||||
|
|
||||||
UART_HW_Uart1_DisableRawRecv:
|
|
||||||
lds r16, UCSR1B
|
|
||||||
; cbr r16, (1<<RXCIE1) ; disable RX complete interrupt
|
|
||||||
andi r16, ~(1<<RXEN1) ; disable receive
|
|
||||||
sts UCSR1B, r16
|
|
||||||
ret
|
|
||||||
; @end
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
; ---------------------------------------------------------------------------
|
|
||||||
; @routine UART_HW_Uart1_RawRecvPacket
|
|
||||||
; Receive packet.
|
|
||||||
;
|
|
||||||
; @param R16 COM address to listen to
|
|
||||||
; @param R17 maximum value for accepted msg data (i.e. buffersize minus 3)
|
|
||||||
; @param R18 max number of secs to wait for incoming message
|
|
||||||
; @param X buffer to receive to
|
|
||||||
; @return CFLAG set if okay (packet received), cleared on error
|
|
||||||
; @return R16 error code if CFLAG is cleared (COM2_ERROR_NOTFORME, COM2_ERROR_IOERROR, COM2_ERROR_DATAERROR)
|
|
||||||
; @clobbers: r16, r17, r18, r19, r22, X
|
|
||||||
|
|
||||||
UART_HW_Uart1_RawRecvPacket:
|
|
||||||
lds r19, UCSR1A
|
|
||||||
cbr r19, (1<<FE1) | (1<<DOR1) | (1<<UPE1)
|
|
||||||
sts UCSR1A, r19 ; clear errors, TODO: flush!!
|
|
||||||
|
|
||||||
; wait for data
|
|
||||||
push r16
|
|
||||||
mov r16, r18
|
|
||||||
rcall uartHwUart1RawWaitForByte ; (r16, r18, r22)
|
|
||||||
pop r16
|
|
||||||
brcc UART_HW_Uart1_RawRecvPacket_error
|
|
||||||
|
|
||||||
; data available, start reading
|
|
||||||
mov r19, r17 ; max msg payload size
|
|
||||||
push r16
|
|
||||||
; read destination address
|
|
||||||
rcall uartHwUart1RawRecvByte ; (R16, R18, R22)
|
|
||||||
pop r17 ; pop acceptable COM address from R16 to R17
|
|
||||||
brcc UART_HW_Uart1_RawRecvPacket_error
|
|
||||||
|
|
||||||
#ifndef COM_ACCEPT_ALL_DEST ; accept every destination address
|
|
||||||
; compare destination address (accept "FF" and own address)
|
|
||||||
cp r16, r17
|
|
||||||
breq UART_HW_Uart1_RawRecvPacket_acceptAddr
|
|
||||||
cpi r16, 0xff
|
|
||||||
breq UART_HW_Uart1_RawRecvPacket_acceptAddr
|
|
||||||
ldi r16, COM2_ERROR_NOTFORME
|
|
||||||
rjmp UART_HW_Uart1_RawRecvPacket_error
|
|
||||||
#endif
|
|
||||||
UART_HW_Uart1_RawRecvPacket_acceptAddr:
|
|
||||||
st X+, r16 ; store destination addr
|
|
||||||
; read msg length
|
|
||||||
rcall uartHwUart1RawRecvByte ; (R16, R18, R22)
|
|
||||||
brcc UART_HW_Uart1_RawRecvPacket_error
|
|
||||||
cp r16, r19 ; (COM2_BUFFER_SIZE-3)
|
|
||||||
brcc UART_HW_Uart1_RawRecvPacket_error
|
|
||||||
tst r16
|
|
||||||
breq UART_HW_Uart1_RawRecvPacket_error
|
|
||||||
st X+, r16
|
|
||||||
inc r16 ; account for checksum byte
|
|
||||||
mov r17, r16
|
|
||||||
; read message content
|
|
||||||
UART_HW_Uart1_RawRecvPacket_loop:
|
|
||||||
rcall uartHwUart1RawRecvByte ; (R16, R18, R22)
|
|
||||||
brcc UART_HW_Uart1_RawRecvPacket_error
|
|
||||||
st X+, r16
|
|
||||||
dec r17
|
|
||||||
brne UART_HW_Uart1_RawRecvPacket_loop
|
|
||||||
sec
|
|
||||||
rjmp UART_HW_Uart1_RawRecvPacket_end
|
|
||||||
UART_HW_Uart1_RawRecvPacket_error:
|
|
||||||
clc
|
|
||||||
UART_HW_Uart1_RawRecvPacket_end:
|
|
||||||
ret
|
|
||||||
; @end
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
; ---------------------------------------------------------------------------
|
|
||||||
; @routine uartHwUart1RawRecvByte
|
|
||||||
; Receive one byte.
|
|
||||||
;
|
|
||||||
; @return CFLAG set if okay, cleared on error
|
|
||||||
; @return R16 error code if CFLAG is cleared
|
|
||||||
; @clobbers: r16 (r18, r22)
|
|
||||||
|
|
||||||
uartHwUart1RawRecvByte:
|
|
||||||
; lds r22, UCSR1A
|
|
||||||
; sbrs r22, RXC1
|
|
||||||
; rjmp uartHwUart1RawRecvByte
|
|
||||||
; lds r16, UDR1
|
|
||||||
; sec
|
|
||||||
; ret
|
|
||||||
|
|
||||||
rcall uartHwUart1RawWaitForByte1ms ; (r18, r22)
|
|
||||||
brcc uartHwUart1RawRecvByte_error
|
|
||||||
lds r16, UCSR1A ; check for errors
|
|
||||||
andi r16, (1<<FE1) | (1<<DOR1) | (1<<UPE1)
|
|
||||||
brne uartHwUart1RawRecvByte_error
|
|
||||||
lds r16, UDR1
|
|
||||||
sec
|
|
||||||
ret
|
|
||||||
uartHwUart1RawRecvByte_error:
|
|
||||||
clc
|
|
||||||
ret
|
|
||||||
; @end
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
; ---------------------------------------------------------------------------
|
|
||||||
; @routine uartHwUart1RawWaitForByte
|
|
||||||
; wait for up to given number of secs for incoming byte
|
|
||||||
;
|
|
||||||
; @return CFLAG set if okay, cleared on error
|
|
||||||
; @param r16 number of secs to wait
|
|
||||||
; @clobbers: r16, r18, r22
|
|
||||||
|
|
||||||
uartHwUart1RawWaitForByte:
|
|
||||||
uartHwUart1RawWaitForByte_loop:
|
|
||||||
rcall uartHwUart1RawWaitForByte1s ; (r18, r22)
|
|
||||||
brcs uartHwUart1RawWaitForByte_haveByte
|
|
||||||
dec r16
|
|
||||||
brne uartHwUart1RawWaitForByte_loop
|
|
||||||
clc
|
|
||||||
uartHwUart1RawWaitForByte_haveByte:
|
|
||||||
ret
|
|
||||||
; @end
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
; ---------------------------------------------------------------------------
|
|
||||||
; @routine uartHwUart1RawWaitForByte1s
|
|
||||||
; wait for up to 1s for incoming byte
|
|
||||||
;
|
|
||||||
; @return CFLAG set if okay, cleared on error
|
|
||||||
; @clobbers: r18, r22
|
|
||||||
|
|
||||||
uartHwUart1RawWaitForByte1s:
|
|
||||||
ldi r18, 10
|
|
||||||
uartHwUart1RawWaitForByte1s_loop:
|
|
||||||
push r18
|
|
||||||
rcall uartHwUart1RawWaitForByte100ms ; (r18, r22)
|
|
||||||
pop r18
|
|
||||||
brcs uartHwUart1RawWaitForByte1s_haveByte
|
|
||||||
sbi LED_SIMPLE_PORTIN, LED_SIMPLE_PINNUM ; toggle
|
|
||||||
dec r18
|
|
||||||
brne uartHwUart1RawWaitForByte1s_loop
|
|
||||||
clc
|
|
||||||
uartHwUart1RawWaitForByte1s_haveByte:
|
|
||||||
ret
|
|
||||||
; @end
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
; ---------------------------------------------------------------------------
|
|
||||||
; @routine uartHwUart1RawWaitForByte100ms
|
|
||||||
; wait for up to 100ms for incoming byte
|
|
||||||
;
|
|
||||||
; @return CFLAG set if okay, cleared on error
|
|
||||||
; @clobbers: r18, r22
|
|
||||||
|
|
||||||
uartHwUart1RawWaitForByte100ms:
|
|
||||||
ldi r18, 100
|
|
||||||
uartHwUart1RawWaitForByte100ms_loop:
|
|
||||||
push r18
|
|
||||||
rcall uartHwUart1RawWaitForByte1ms ; (r18, r22)
|
|
||||||
pop r18
|
|
||||||
brcs uartHwUart1RawWaitForByte100ms_haveByte
|
|
||||||
dec r18
|
|
||||||
brne uartHwUart1RawWaitForByte100ms_loop
|
|
||||||
clc
|
|
||||||
uartHwUart1RawWaitForByte100ms_haveByte:
|
|
||||||
ret
|
|
||||||
; @end
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
; ---------------------------------------------------------------------------
|
|
||||||
; @routine uartHwUart1RawWaitForByte1ms
|
|
||||||
; wait for up to 1ms for incoming byte
|
|
||||||
;
|
|
||||||
; @return CFLAG set if okay, cleared on error
|
|
||||||
; @clobbers: r18, r22
|
|
||||||
|
|
||||||
uartHwUart1RawWaitForByte1ms:
|
|
||||||
ldi r18, 100
|
|
||||||
uartHwUart1RawWaitForByte1ms_loop:
|
|
||||||
lds r22, UCSR1A
|
|
||||||
sbrc r22, RXC1
|
|
||||||
rjmp uartHwUart1RawWaitForByte1ms_haveByte
|
|
||||||
rcall Utils_WaitFor10MicroSecs ; wait for 10us (R22)
|
|
||||||
dec r18
|
|
||||||
brne uartHwUart1RawWaitForByte1ms_loop
|
|
||||||
clc
|
|
||||||
ret
|
|
||||||
uartHwUart1RawWaitForByte1ms_haveByte:
|
|
||||||
sec
|
|
||||||
ret
|
|
||||||
; @end
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
.equ COMIO_RawSendPacket = UART_HW_Uart1_RawSendPacket
|
|
||||||
.equ COMIO_RawRecvPacket = UART_HW_Uart1_RawRecvPacket
|
|
||||||
.equ COMIO_EnableRawRecv = UART_HW_Uart1_EnableRawRecv
|
|
||||||
.equ COMIO_DisableRawRecv = UART_HW_Uart1_DisableRawRecv
|
|
||||||
|
|
||||||
|
|
||||||
@@ -29,7 +29,8 @@ ttyOnUart1_iface: .byte UART_HW_IFACE_SIZE
|
|||||||
TtyOnUart1_Init:
|
TtyOnUart1_Init:
|
||||||
ldi yl, LOW(ttyOnUart1_iface)
|
ldi yl, LOW(ttyOnUart1_iface)
|
||||||
ldi yh, HIGH(ttyOnUart1_iface)
|
ldi yh, HIGH(ttyOnUart1_iface)
|
||||||
rcall UART_HW_Uart1_Init ; (R16, R17, X)
|
rcall UART_HW_InterfaceInit ; (R16, R17, X)
|
||||||
|
rcall UART_HW_Uart1_Init ; (R16, R17, X)
|
||||||
ldi r16, TTYONUART1_IFACENUM
|
ldi r16, TTYONUART1_IFACENUM
|
||||||
std Y+UART_HW_IFACE_OFFS_IFACENUM, r16
|
std Y+UART_HW_IFACE_OFFS_IFACENUM, r16
|
||||||
ldi r16, UART_HW_MODE_IDLE | UART_HW_MODE_W_IDLE ; start in full idle mode
|
ldi r16, UART_HW_MODE_IDLE | UART_HW_MODE_W_IDLE ; start in full idle mode
|
||||||
@@ -182,7 +183,7 @@ TtyOnUart1_Run:
|
|||||||
|
|
||||||
ttyOnUart1RunWriteModes:
|
ttyOnUart1RunWriteModes:
|
||||||
ldd r16, Y+UART_HW_IFACE_OFFS_MODE ; handle write functions
|
ldd r16, Y+UART_HW_IFACE_OFFS_MODE ; handle write functions
|
||||||
cbr r16, UART_HW_MODE_READMASK
|
andi r16, UART_HW_MODE_WRITEMASK
|
||||||
cpi r16, UART_HW_MODE_W_IDLE
|
cpi r16, UART_HW_MODE_W_IDLE
|
||||||
breq ttyOnUart1RunWIdle
|
breq ttyOnUart1RunWIdle
|
||||||
cpi r16, UART_HW_MODE_WRITING
|
cpi r16, UART_HW_MODE_WRITING
|
||||||
@@ -271,7 +272,7 @@ ttyOnUart1RunWriteBufferEmpty:
|
|||||||
|
|
||||||
ttyOnUart1RunReadModes:
|
ttyOnUart1RunReadModes:
|
||||||
ldd r16, Y+UART_HW_IFACE_OFFS_MODE ; handle read functions
|
ldd r16, Y+UART_HW_IFACE_OFFS_MODE ; handle read functions
|
||||||
cbr r16, UART_HW_MODE_WRITEMASK
|
andi r16, UART_HW_MODE_READMASK
|
||||||
cpi r16, UART_HW_MODE_IDLE
|
cpi r16, UART_HW_MODE_IDLE
|
||||||
breq ttyOnUart1RunIdle
|
breq ttyOnUart1RunIdle
|
||||||
cpi r16, UART_HW_MODE_READING
|
cpi r16, UART_HW_MODE_READING
|
||||||
|
|||||||
Reference in New Issue
Block a user