martin/aqhomecontrol
Public Access
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

avr: more work on t03 and hw uart modules.

Browse Source 
Too complicated, will start new...
This commit is contained in:
Martin Preuss
2025-02-10 23:36:52 +01:00
parent 358ceaaa7d
commit 0790ac0dea
6 changed files with 165 additions and 347 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
avr/modules/uart_hw/defs.asm
View File

@@ -26,9 +26,9 @@
.equ UART_HW_MODE_SKIPPING = 3
.equ UART_HW_MODE_W_IDLE = 0
.equ UART_HW_MODE_WRITING = 8
.equ UART_HW_MODE_WAITBUFFEREMPTY = 9
.equ UART_HW_MODE_WRITEBUFFEREMPTY = 10
.equ UART_HW_MODE_WRITING = 16
.equ UART_HW_MODE_WAITBUFFEREMPTY = 17
.equ UART_HW_MODE_WRITEBUFFEREMPTY = 18
.equ UART_HW_STATUS_UNDERRUN_BIT = 0

12
avr/modules/uart_hw/lowlevel.asm
View File

@@ -58,25 +58,31 @@ UART_HW_InterfaceInit:
clr r16
rcall Utils_FillSram ; (R17, X)
; reset ringbuffer for recvd chars
m_ringbuffer_y_reset UART_HW_IFACE_READBUF_SIZE, \
m_ringbuffer_y_reset UART_HW_IFACE_OFFS_READBUF_MAX, \
UART_HW_IFACE_OFFS_READBUF_USED, \
UART_HW_IFACE_OFFS_READBUF_RDPOS, \
UART_HW_IFACE_OFFS_READBUF_WRPOS, \
UART_HW_IFACE_OFFS_READBUF_DATA
ldi r16, UART_HW_IFACE_READBUF_SIZE
std Y+UART_HW_IFACE_OFFS_READBUF_MAX, r16
; reset ringbuffer for chars to transmit
m_ringbuffer_y_reset UART_HW_IFACE_WRITEBUF_SIZE, \
m_ringbuffer_y_reset UART_HW_IFACE_OFFS_WRITEBUF_MAX, \
UART_HW_IFACE_OFFS_WRITEBUF_USED, \
UART_HW_IFACE_OFFS_WRITEBUF_RDPOS, \
UART_HW_IFACE_OFFS_WRITEBUF_WRPOS, \
UART_HW_IFACE_OFFS_WRITEBUF_DATA
ldi r16, UART_HW_IFACE_WRITEBUF_SIZE
std Y+UART_HW_IFACE_OFFS_WRITEBUF_MAX, r16
; reset ringbuffer for messages to be sent
m_ringbuffer_y_reset UART_HW_IFACE_OUTMSGBUF_SIZE, \
m_ringbuffer_y_reset UART_HW_IFACE_OFFS_OUTMSGBUF_MAX, \
UART_HW_IFACE_OFFS_OUTMSGBUF_USED, \
UART_HW_IFACE_OFFS_OUTMSGBUF_RDPOS, \
UART_HW_IFACE_OFFS_OUTMSGBUF_WRPOS, \
UART_HW_IFACE_OFFS_OUTMSGBUF_DATA
ldi r16, UART_HW_IFACE_OUTMSGBUF_SIZE
std Y+UART_HW_IFACE_OFFS_OUTMSGBUF_MAX, r16
ldi r16, 0xff
std Y+UART_HW_IFACE_OFFS_READMSG_BUFNUM, r16

3
avr/modules/uart_hw/msglevel_send.asm
View File

@@ -87,13 +87,14 @@ uartHwWriteUptoNumBytes:
ldd xl, Y+UART_HW_IFACE_OFFS_WRITEMSG_PTR
ldd xh, Y+UART_HW_IFACE_OFFS_WRITEMSG_PTR+1
uartHwWriteUptoNumBytes_loop:
ld r16, X+
ld r16, X
push xl
push xh
rcall UART_HW_InterfaceWriteToWriteBuffer ; (R17, R18, X)
pop xh
pop xl
brcc uartHwWriteUptoNumBytes_done
adiw xh:xl, 1
inc r21
dec r20
brne uartHwWriteUptoNumBytes_loop

319
avr/modules/uart_hw/raw_uart1.asm
View File

@@ -1,319 +0,0 @@
; ***************************************************************************
; copyright : (C) 2025 by Martin Preuss
; email : martin@libchipcard.de
;
; ***************************************************************************
; * This file is part of the project "AqHome". *
; * Please see toplevel file COPYING of that project for license details. *
; ***************************************************************************
; ---------------------------------------------------------------------------
; @routine UART_HW_Uart1_RawInit @global
;
; @clobbers R16, R17
UART_HW_Uart1_RawInit:
; set baudrate
.if clock == 8000000
ldi r16, 25 ; (19.2Kb/s at 8MHz)
ldi r17, 0
.endif
.if clock == 1000000
ldi r16, 3 ; (19.2Kb/s at 1MHz)
ldi r17, 0
.endif
sts UBRR1H, r17
sts UBRR1L, r16
; set character format (asynchronous USART, 8-bit, one stop bit, no parity)
ldi r16, (3<<UCSZ10)
sts UCSR1C, r16
ret
; @end
; ---------------------------------------------------------------------------
; @routine UART_HW_Uart1_RawSendPacket
; Send packet.
;
; @param X buffer to send
; @return CFLAG: set if okay (packet sent), cleared on error
; @clobbers r16, r17, X
UART_HW_Uart1_RawSendPacket:
adiw xh:xl, 1
ld r17, X
sbiw xh:xl, 1
ldi r16, 3 ; add DEST, LEN, CRC bytes
add r17, r16
lds r16, UCSR1B
; cbr r16, (1<<UDRIE1) ; disable DRE interrupt
sbr r16, (1<<TXEN1) ; enable transmit
sts UCSR1B, r16
;; clr r16 ; clear all pending interrupts
;; sts UCSR1A, r16
;ldi r17, 20
UART_HW_Uart1_RawSendPacket_loop:
lds r16, UCSR1A
sbrs r16, UDRE1
rjmp UART_HW_Uart1_RawSendPacket_loop
sbr r16, (1<<TXC1)
sts UCSR1A, r16
ld r16, X+
sts UDR1, r16
dec r17
brne UART_HW_Uart1_RawSendPacket_loop
; disable transmit
; lds r16, UCSR1B
; cbr r16, (1<<TXEN1) ; disable transmit
; sts UCSR1B, r16
sec
ret
; @end
; ---------------------------------------------------------------------------
; @routine UART_HW_Uart1_EnableRawRecv @global
;
; Enable receiving messages in raw mode.
;
; @clobbers: r16
UART_HW_Uart1_EnableRawRecv:
lds r16, UCSR1B
; cbr r16, (1<<RXCIE1) ; disable RX complete interrupt
ori r16, (1<<RXEN1) ; enable receive
sts UCSR1B, r16
ret
; @end
; ---------------------------------------------------------------------------
; @routine UART_HW_Uart1_DisableRawRecv @global
;
; Disable receiving messages in raw mode.
;
; @clobbers: r16
UART_HW_Uart1_DisableRawRecv:
lds r16, UCSR1B
; cbr r16, (1<<RXCIE1) ; disable RX complete interrupt
andi r16, ~(1<<RXEN1) ; disable receive
sts UCSR1B, r16
ret
; @end
; ---------------------------------------------------------------------------
; @routine UART_HW_Uart1_RawRecvPacket
; Receive packet.
;
; @param R16 COM address to listen to
; @param R17 maximum value for accepted msg data (i.e. buffersize minus 3)
; @param R18 max number of secs to wait for incoming message
; @param X buffer to receive to
; @return CFLAG set if okay (packet received), cleared on error
; @return R16 error code if CFLAG is cleared (COM2_ERROR_NOTFORME, COM2_ERROR_IOERROR, COM2_ERROR_DATAERROR)
; @clobbers: r16, r17, r18, r19, r22, X
UART_HW_Uart1_RawRecvPacket:
lds r19, UCSR1A
cbr r19, (1<<FE1) | (1<<DOR1) | (1<<UPE1)
sts UCSR1A, r19 ; clear errors, TODO: flush!!
; wait for data
push r16
mov r16, r18
rcall uartHwUart1RawWaitForByte ; (r16, r18, r22)
pop r16
brcc UART_HW_Uart1_RawRecvPacket_error
; data available, start reading
mov r19, r17 ; max msg payload size
push r16
; read destination address
rcall uartHwUart1RawRecvByte ; (R16, R18, R22)
pop r17 ; pop acceptable COM address from R16 to R17
brcc UART_HW_Uart1_RawRecvPacket_error
#ifndef COM_ACCEPT_ALL_DEST ; accept every destination address
; compare destination address (accept "FF" and own address)
cp r16, r17
breq UART_HW_Uart1_RawRecvPacket_acceptAddr
cpi r16, 0xff
breq UART_HW_Uart1_RawRecvPacket_acceptAddr
ldi r16, COM2_ERROR_NOTFORME
rjmp UART_HW_Uart1_RawRecvPacket_error
#endif
UART_HW_Uart1_RawRecvPacket_acceptAddr:
st X+, r16 ; store destination addr
; read msg length
rcall uartHwUart1RawRecvByte ; (R16, R18, R22)
brcc UART_HW_Uart1_RawRecvPacket_error
cp r16, r19 ; (COM2_BUFFER_SIZE-3)
brcc UART_HW_Uart1_RawRecvPacket_error
tst r16
breq UART_HW_Uart1_RawRecvPacket_error
st X+, r16
inc r16 ; account for checksum byte
mov r17, r16
; read message content
UART_HW_Uart1_RawRecvPacket_loop:
rcall uartHwUart1RawRecvByte ; (R16, R18, R22)
brcc UART_HW_Uart1_RawRecvPacket_error
st X+, r16
dec r17
brne UART_HW_Uart1_RawRecvPacket_loop
sec
rjmp UART_HW_Uart1_RawRecvPacket_end
UART_HW_Uart1_RawRecvPacket_error:
clc
UART_HW_Uart1_RawRecvPacket_end:
ret
; @end
; ---------------------------------------------------------------------------
; @routine uartHwUart1RawRecvByte
; Receive one byte.
;
; @return CFLAG set if okay, cleared on error
; @return R16 error code if CFLAG is cleared
; @clobbers: r16 (r18, r22)
uartHwUart1RawRecvByte:
; lds r22, UCSR1A
; sbrs r22, RXC1
; rjmp uartHwUart1RawRecvByte
; lds r16, UDR1
; sec
; ret
rcall uartHwUart1RawWaitForByte1ms ; (r18, r22)
brcc uartHwUart1RawRecvByte_error
lds r16, UCSR1A ; check for errors
andi r16, (1<<FE1) | (1<<DOR1) | (1<<UPE1)
brne uartHwUart1RawRecvByte_error
lds r16, UDR1
sec
ret
uartHwUart1RawRecvByte_error:
clc
ret
; @end
; ---------------------------------------------------------------------------
; @routine uartHwUart1RawWaitForByte
; wait for up to given number of secs for incoming byte
;
; @return CFLAG set if okay, cleared on error
; @param r16 number of secs to wait
; @clobbers: r16, r18, r22
uartHwUart1RawWaitForByte:
uartHwUart1RawWaitForByte_loop:
rcall uartHwUart1RawWaitForByte1s ; (r18, r22)
brcs uartHwUart1RawWaitForByte_haveByte
dec r16
brne uartHwUart1RawWaitForByte_loop
clc
uartHwUart1RawWaitForByte_haveByte:
ret
; @end
; ---------------------------------------------------------------------------
; @routine uartHwUart1RawWaitForByte1s
; wait for up to 1s for incoming byte
;
; @return CFLAG set if okay, cleared on error
; @clobbers: r18, r22
uartHwUart1RawWaitForByte1s:
ldi r18, 10
uartHwUart1RawWaitForByte1s_loop:
push r18
rcall uartHwUart1RawWaitForByte100ms ; (r18, r22)
pop r18
brcs uartHwUart1RawWaitForByte1s_haveByte
sbi LED_SIMPLE_PORTIN, LED_SIMPLE_PINNUM ; toggle
dec r18
brne uartHwUart1RawWaitForByte1s_loop
clc
uartHwUart1RawWaitForByte1s_haveByte:
ret
; @end
; ---------------------------------------------------------------------------
; @routine uartHwUart1RawWaitForByte100ms
; wait for up to 100ms for incoming byte
;
; @return CFLAG set if okay, cleared on error
; @clobbers: r18, r22
uartHwUart1RawWaitForByte100ms:
ldi r18, 100
uartHwUart1RawWaitForByte100ms_loop:
push r18
rcall uartHwUart1RawWaitForByte1ms ; (r18, r22)
pop r18
brcs uartHwUart1RawWaitForByte100ms_haveByte
dec r18
brne uartHwUart1RawWaitForByte100ms_loop
clc
uartHwUart1RawWaitForByte100ms_haveByte:
ret
; @end
; ---------------------------------------------------------------------------
; @routine uartHwUart1RawWaitForByte1ms
; wait for up to 1ms for incoming byte
;
; @return CFLAG set if okay, cleared on error
; @clobbers: r18, r22
uartHwUart1RawWaitForByte1ms:
ldi r18, 100
uartHwUart1RawWaitForByte1ms_loop:
lds r22, UCSR1A
sbrc r22, RXC1
rjmp uartHwUart1RawWaitForByte1ms_haveByte
rcall Utils_WaitFor10MicroSecs ; wait for 10us (R22)
dec r18
brne uartHwUart1RawWaitForByte1ms_loop
clc
ret
uartHwUart1RawWaitForByte1ms_haveByte:
sec
ret
; @end
.equ COMIO_RawSendPacket = UART_HW_Uart1_RawSendPacket
.equ COMIO_RawRecvPacket = UART_HW_Uart1_RawRecvPacket
.equ COMIO_EnableRawRecv = UART_HW_Uart1_EnableRawRecv
.equ COMIO_DisableRawRecv = UART_HW_Uart1_DisableRawRecv

7
avr/modules/uart_hw/ttyonuart1.asm
View File

@@ -29,7 +29,8 @@ ttyOnUart1_iface: .byte UART_HW_IFACE_SIZE
TtyOnUart1_Init:
ldi yl, LOW(ttyOnUart1_iface)
ldi yh, HIGH(ttyOnUart1_iface)
rcall UART_HW_Uart1_Init ; (R16, R17, X)
rcall UART_HW_InterfaceInit ; (R16, R17, X)
rcall UART_HW_Uart1_Init ; (R16, R17, X)
ldi r16, TTYONUART1_IFACENUM
std Y+UART_HW_IFACE_OFFS_IFACENUM, r16
ldi r16, UART_HW_MODE_IDLE | UART_HW_MODE_W_IDLE ; start in full idle mode
@@ -182,7 +183,7 @@ TtyOnUart1_Run:
ttyOnUart1RunWriteModes:
ldd r16, Y+UART_HW_IFACE_OFFS_MODE ; handle write functions
cbr r16, UART_HW_MODE_READMASK
andi r16, UART_HW_MODE_WRITEMASK
cpi r16, UART_HW_MODE_W_IDLE
breq ttyOnUart1RunWIdle
cpi r16, UART_HW_MODE_WRITING
@@ -271,7 +272,7 @@ ttyOnUart1RunWriteBufferEmpty:
ttyOnUart1RunReadModes:
ldd r16, Y+UART_HW_IFACE_OFFS_MODE ; handle read functions
cbr r16, UART_HW_MODE_WRITEMASK
andi r16, UART_HW_MODE_READMASK
cpi r16, UART_HW_MODE_IDLE
breq ttyOnUart1RunIdle
cpi r16, UART_HW_MODE_READING